qemu/include/hw/net
Peter Maydell f00f57f344 This PR includes multiple fixes and features for RISC-V:
- Fixes a bug in printing trap causes
  - Allows 16-bit writes to the SiFive test device. This fixes the
    failure to reboot the RISC-V virt machine
  - Support for the Microchip PolarFire SoC and Icicle Kit
  - A reafactor of RISC-V code out of hw/riscv
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging

This PR includes multiple fixes and features for RISC-V:
 - Fixes a bug in printing trap causes
 - Allows 16-bit writes to the SiFive test device. This fixes the
   failure to reboot the RISC-V virt machine
 - Support for the Microchip PolarFire SoC and Icicle Kit
 - A reafactor of RISC-V code out of hw/riscv

# gpg: Signature made Thu 10 Sep 2020 19:08:06 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits)
  hw/riscv: Sort the Kconfig options in alphabetical order
  hw/riscv: Drop CONFIG_SIFIVE
  hw/riscv: Always build riscv_hart.c
  hw/riscv: Move sifive_test model to hw/misc
  hw/riscv: Move sifive_uart model to hw/char
  hw/riscv: Move riscv_htif model to hw/char
  hw/riscv: Move sifive_plic model to hw/intc
  hw/riscv: Move sifive_clint model to hw/intc
  hw/riscv: Move sifive_gpio model to hw/gpio
  hw/riscv: Move sifive_u_otp model to hw/misc
  hw/riscv: Move sifive_u_prci model to hw/misc
  hw/riscv: Move sifive_e_prci model to hw/misc
  hw/riscv: sifive_u: Connect a DMA controller
  hw/riscv: clint: Avoid using hard-coded timebase frequency
  hw/riscv: microchip_pfsoc: Hook GPIO controllers
  hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
  hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
  hw/net: cadence_gem: Add a new 'phy-addr' property
  hw/riscv: microchip_pfsoc: Connect a DMA controller
  hw/dma: Add SiFive platform DMA controller emulation
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	hw/riscv/trace-events
2020-09-13 20:29:35 +01:00
..
allwinner_emac.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
allwinner-sun8i-emac.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
cadence_gem.h This PR includes multiple fixes and features for RISC-V: 2020-09-13 20:29:35 +01:00
ftgmac100.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
imx_fec.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
lan9118.h Include hw/irq.h a lot less 2019-08-16 13:31:52 +02:00
lance.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
lasi_82596.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
mii.h net: add Sun HME (Happy Meal Ethernet) on-board NIC 2017-09-21 08:38:42 +01:00
msf2-emac.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
ne2000-isa.h isa: Convert uses of isa_create(), isa_try_create() manually 2020-06-15 22:05:28 +02:00
smc91c111.h Include hw/irq.h a lot less 2019-08-16 13:31:52 +02:00