Alistair Francis 32c435a1ae hw/riscv: boot: Don't use CSRs if they are disabled ... If the CSRs and CSR instructions are disabled because the Zicsr extension isn't enabled then we want to make sure we don't run any CSR instructions in the boot ROM. This patches removes the CSR instructions from the reset-vec if the extension isn't enabled. We replace the instruction with a NOP instead. Note that we don't do this for the SiFive U machine, as we are modelling the hardware in that case. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-02-07 08:19:22 +10:00
..
boot.c	hw/riscv: boot: Don't use CSRs if they are disabled	2023-02-07 08:19:22 +10:00
Kconfig	hw/riscv: Sort machines Kconfig options in alphabetical order	2023-01-06 10:42:55 +10:00
meson.build	hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines	2021-07-20 15:32:49 +02:00
microchip_pfsoc.c	hw/riscv/boot.c: use MachineState in riscv_load_kernel()	2023-01-20 10:14:13 +10:00
numa.c	hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()	2023-01-20 10:14:14 +10:00
opentitan.c	include/hw/riscv/opentitan: update opentitan IRQs	2023-02-07 08:19:22 +10:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()	2022-09-07 09:18:33 +02:00
sifive_e.c	hw/riscv/boot.c: use MachineState in riscv_load_kernel()	2023-01-20 10:14:13 +10:00
sifive_u.c	hw/riscv/sifive_u.c: simplify create_fdt()	2023-01-20 10:14:14 +10:00
spike.c	hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()	2023-01-20 10:14:14 +10:00
virt.c	hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init()	2023-01-20 10:14:14 +10:00