48fbcf5c6c
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230227135202.9710-10-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
51 lines
1.2 KiB
C
51 lines
1.2 KiB
C
/*
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* ARM cpu parameters for qemu.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* SPDX-License-Identifier: LGPL-2.0+
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*/
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#ifndef ARM_CPU_PARAM_H
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#define ARM_CPU_PARAM_H
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#ifdef TARGET_AARCH64
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# define TARGET_LONG_BITS 64
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# define TARGET_PHYS_ADDR_SPACE_BITS 52
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# define TARGET_VIRT_ADDR_SPACE_BITS 52
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#else
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# define TARGET_LONG_BITS 32
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# define TARGET_PHYS_ADDR_SPACE_BITS 40
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif
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#ifdef CONFIG_USER_ONLY
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#define TARGET_PAGE_BITS 12
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# ifdef TARGET_AARCH64
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# define TARGET_TAGGED_ADDRESSES
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# endif
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#else
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/*
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* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
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* have to support 1K tiny pages.
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*/
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# define TARGET_PAGE_BITS_VARY
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# define TARGET_PAGE_BITS_MIN 10
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/*
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* Cache the attrs and shareability fields from the page table entry.
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*
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* For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2].
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* Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format.
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* For shareability and guarded, as in the SH and GP fields respectively
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* of the VMSAv8-64 PTEs.
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*/
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# define TARGET_PAGE_ENTRY_EXTRA \
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uint8_t pte_attrs; \
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uint8_t shareability; \
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bool guarded;
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#endif
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#define NB_MMU_MODES 12
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#endif
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