qemu/target
Paolo Bonzini c46f68bd7d target/i386: pcrel: store low bits of physical address in data[0]
For PC-relative translation blocks, env->eip changes during the
execution of a translation block, Therefore, QEMU must be able to
recover an instruction's PC just from the TranslationBlock struct and
the instruction data with.  Because a TB will not span two pages, QEMU
stores all the low bits of EIP in the instruction data and replaces them
in x86_restore_state_to_opc.  Bits 12 and higher (which may vary between
executions of a PCREL TB, since these only use the physical address in
the hash key) are kept unmodified from env->eip.  The assumption is that
these bits of EIP, unlike bits 0-11, will not change as the translation
block executes.

Unfortunately, this is incorrect when the CS base is not aligned to a page.
Then the linear address of the instructions (i.e. the one with the
CS base addred) indeed will never span two pages, but bits 12+ of EIP
can actually change.  For example, if CS base is 0x80262200 and EIP =
0x6FF4, the first instruction in the translation block will be at linear
address 0x802691F4.  Even a very small TB will cross to EIP = 0x7xxx,
while the linear addresses will remain comfortably within a single page.

The fix is simply to use the low bits of the linear address for data[0],
since those don't change.  Then x86_restore_state_to_opc uses tb->cs_base
to compute a temporary linear address (referring to some unknown
instruction in the TB, but with the correct values of bits 12 and higher);
the low bits are replaced with data[0], and EIP is obtained by subtracting
again the CS base.

Huge thanks to Mark Cave-Ayland for the image and initial debugging,
and to Gitlab user @kjliew for help with bisecting another occurrence
of (hopefully!) the same bug.

It should be relatively easy to write a testcase that performs MMIO on
an EIP with different bits 12+ than the first instruction of the translation
block; any help is welcome.

Fixes: e3a79e0e87 ("target/i386: Enable TARGET_TB_PCREL", 2022-10-11)
Cc: qemu-stable@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1759
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1964
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2012
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit 729ba8e933)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-20 12:24:50 +03:00
..
alpha hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
arm target/arm: Disable SME if SVE is disabled 2023-12-04 13:34:16 +00:00
avr hw/avr/atmega: Fix wrong initial value of stack pointer 2023-11-28 14:27:12 +01:00
cris hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
hexagon target/hexagon/idef-parser/prepare: use env to invoke bash 2023-11-28 14:26:37 +01:00
hppa target/hppa: Fix IOR and ISR on error in probe 2024-01-17 10:32:47 +03:00
i386 target/i386: pcrel: store low bits of physical address in data[0] 2024-01-20 12:24:50 +03:00
loongarch hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
m68k hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
microblaze target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
mips target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
nios2 target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
openrisc hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
ppc target/ppc: Fix bugs in VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2 macros 2023-11-21 08:39:58 +01:00
riscv target/riscv: Fix mcycle/minstret increment behavior 2024-01-08 19:24:31 +03:00
rx hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
s390x target/s390x: Fix LAE setting a wrong access register 2024-01-13 11:20:14 +03:00
sh4 sh4: Coding style: Remove tabs 2023-12-04 15:12:57 +01:00
sparc target/sparc: Fix RETURN 2023-11-14 10:40:54 -08:00
tricore hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
xtensa hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00