Alistair Francis ef63100648 hw/riscv: opentitan: Update to the latest build ... Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com		2021-10-22 23:35:47 +10:00
..
boot.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
Kconfig	hw/intc: Rename sifive_clint sources to riscv_aclint sources	2021-09-21 07:56:49 +10:00
meson.build	hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines	2021-07-20 15:32:49 +02:00
microchip_pfsoc.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
numa.c	hw: Do not include qemu/log.h if it is not necessary	2021-05-02 17:24:50 +02:00
opentitan.c	hw/riscv: opentitan: Update to the latest build	2021-10-22 23:35:47 +10:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv: shakti_c: Mark as not user creatable	2021-10-07 08:41:33 +10:00
sifive_e.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
sifive_u.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
spike.c	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	2021-09-21 07:56:49 +10:00
virt.c	hw/riscv: virt: Use machine->ram as the system memory	2021-10-22 07:47:51 +10:00