qemu/target/arm
Emilio G. Cota 5ca66278c8 arm/translate-a64: mark path as unreachable to eliminate warning
Fixes the following warning when compiling with gcc 5.4.0 with -O1
optimizations and --enable-debug:

target/arm/translate-a64.c: In function ‘aarch64_tr_translate_insn’:
target/arm/translate-a64.c:2361:8: error: ‘post_index’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
     if (!post_index) {
        ^
target/arm/translate-a64.c:2307:10: note: ‘post_index’ was declared here
     bool post_index;
          ^
target/arm/translate-a64.c:2386:8: error: ‘writeback’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
     if (writeback) {
        ^
target/arm/translate-a64.c:2308:10: note: ‘writeback’ was declared here
     bool writeback;
          ^

Note that idx comes from selecting 2 bits, and therefore its value
can be at most 3.

Signed-off-by: Emilio G. Cota <cota@braap.org>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1510087611-1851-1-git-send-email-cota@braap.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-11-13 13:55:24 +00:00
..
arch_dump.c hmp: fix "dump-quest-memory" segfault (arm) 2017-09-14 15:52:10 +01:00
arm_ldst.h Fix Thumb-1 BE32 execution and disassembly. 2017-02-07 18:29:59 +00:00
arm-powerctl.c target-arm/powerctl: defer cpu reset work to CPU context 2017-02-24 10:32:46 +00:00
arm-powerctl.h target-arm/powerctl: defer cpu reset work to CPU context 2017-02-24 10:32:46 +00:00
arm-semi.c
cpu64.c target-arm: Enable EL2 feature bit on A53 and A57 2017-01-20 11:15:10 +00:00
cpu-qom.h
cpu.c disas: Dump insn bytes along with capstone disassembly 2017-11-09 08:46:38 +01:00
cpu.h target/arm: Factor out "get mmuidx for specified security state" 2017-10-06 16:46:49 +01:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c target/arm: check CF_PARALLEL instead of parallel_cpus 2017-10-24 13:53:41 -07:00
helper-a64.h target/arm: check CF_PARALLEL instead of parallel_cpus 2017-10-24 13:53:41 -07:00
helper.c arm: implement cache/shareability attribute bits for PAR registers 2017-11-07 13:03:51 +00:00
helper.h fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
internals.h fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
iwmmxt_helper.c
kvm32.c target/arm/kvm: pmu: improve error handling 2017-09-04 15:21:54 +01:00
kvm64.c target/arm/kvm: pmu: improve error handling 2017-09-04 15:21:54 +01:00
kvm_arm.h target/arm/kvm: pmu: improve error handling 2017-09-04 15:21:54 +01:00
kvm-consts.h arm: add trailing ; after MISMATCH_CHECK 2017-02-01 03:37:18 +02:00
kvm-stub.c
kvm.c hw/arm/virt: allow pmu instantiation with userspace irqchip 2017-09-04 15:21:54 +01:00
machine.c nvic: Implement Security Attribution Unit registers 2017-10-06 16:46:49 +01:00
Makefile.objs
monitor.c
neon_helper.c
op_addsub.h
op_helper.c fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
psci.c fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
trace-events trace-events: fix code style: print 0x before hex numbers 2017-08-01 12:13:07 +01:00
translate-a64.c arm/translate-a64: mark path as unreachable to eliminate warning 2017-11-13 13:55:24 +00:00
translate.c translate.c: Fix usermode big-endian AArch32 LDREXD and STREXD 2017-11-07 13:03:51 +00:00
translate.h tcg: Initialize cpu_env generically 2017-10-24 13:53:42 -07:00