9bfc04f9ef
The POP states that for a list directed IPL the IPLB is stored into memory by the machine loader and its address is stored at offset 0x14 of the lowcore. ZIPL currently uses the address in offset 0x14 to access the IPLB and acquire flags about secure boot. If the IPLB address points into memory which has an unsupported mix of flags set, ZIPL will panic instead of booting the OS. As the lowcore can have quite a high entropy for a guest that did drop out of protected mode (i.e. rebooted) we encountered the ZIPL panic quite often. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Tested-by: Marc Hartmayer <mhartmay@linux.ibm.com> Message-Id: <20200304114231.23493-19-frankja@linux.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
110 lines
4.3 KiB
C
110 lines
4.3 KiB
C
/*
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* S390 Basic Architecture
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*
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* Copyright (c) 2019 Jason J. Herne <jjherne@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at
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* your option) any later version. See the COPYING file in the top-level
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* directory.
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*/
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#ifndef S390_ARCH_H
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#define S390_ARCH_H
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typedef struct PSW {
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uint64_t mask;
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uint64_t addr;
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} __attribute__ ((aligned(8))) PSW;
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_Static_assert(sizeof(struct PSW) == 16, "PSW size incorrect");
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/* Older PSW format used by LPSW instruction */
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typedef struct PSWLegacy {
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uint32_t mask;
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uint32_t addr;
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} __attribute__ ((aligned(8))) PSWLegacy;
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_Static_assert(sizeof(struct PSWLegacy) == 8, "PSWLegacy size incorrect");
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/* s390 psw bit masks */
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#define PSW_MASK_IOINT 0x0200000000000000ULL
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#define PSW_MASK_WAIT 0x0002000000000000ULL
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#define PSW_MASK_EAMODE 0x0000000100000000ULL
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#define PSW_MASK_BAMODE 0x0000000080000000ULL
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#define PSW_MASK_ZMODE (PSW_MASK_EAMODE | PSW_MASK_BAMODE)
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/* Low core mapping */
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typedef struct LowCore {
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/* prefix area: defined by architecture */
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PSWLegacy ipl_psw; /* 0x000 */
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uint32_t ccw1[2]; /* 0x008 */
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union {
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uint32_t ccw2[2]; /* 0x010 */
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struct {
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uint32_t reserved10;
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uint32_t ptr_iplb;
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};
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};
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uint8_t pad1[0x80 - 0x18]; /* 0x018 */
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uint32_t ext_params; /* 0x080 */
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uint16_t cpu_addr; /* 0x084 */
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uint16_t ext_int_code; /* 0x086 */
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uint16_t svc_ilen; /* 0x088 */
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uint16_t svc_code; /* 0x08a */
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uint16_t pgm_ilen; /* 0x08c */
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uint16_t pgm_code; /* 0x08e */
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uint32_t data_exc_code; /* 0x090 */
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uint16_t mon_class_num; /* 0x094 */
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uint16_t per_perc_atmid; /* 0x096 */
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uint64_t per_address; /* 0x098 */
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uint8_t exc_access_id; /* 0x0a0 */
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uint8_t per_access_id; /* 0x0a1 */
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uint8_t op_access_id; /* 0x0a2 */
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uint8_t ar_access_id; /* 0x0a3 */
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uint8_t pad2[0xA8 - 0xA4]; /* 0x0a4 */
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uint64_t trans_exc_code; /* 0x0a8 */
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uint64_t monitor_code; /* 0x0b0 */
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uint16_t subchannel_id; /* 0x0b8 */
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uint16_t subchannel_nr; /* 0x0ba */
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uint32_t io_int_parm; /* 0x0bc */
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uint32_t io_int_word; /* 0x0c0 */
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uint8_t pad3[0xc8 - 0xc4]; /* 0x0c4 */
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uint32_t stfl_fac_list; /* 0x0c8 */
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uint8_t pad4[0xe8 - 0xcc]; /* 0x0cc */
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uint64_t mcic; /* 0x0e8 */
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uint8_t pad5[0xf4 - 0xf0]; /* 0x0f0 */
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uint32_t external_damage_code; /* 0x0f4 */
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uint64_t failing_storage_address; /* 0x0f8 */
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uint8_t pad6[0x110 - 0x100]; /* 0x100 */
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uint64_t per_breaking_event_addr; /* 0x110 */
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uint8_t pad7[0x120 - 0x118]; /* 0x118 */
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PSW restart_old_psw; /* 0x120 */
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PSW external_old_psw; /* 0x130 */
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PSW svc_old_psw; /* 0x140 */
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PSW program_old_psw; /* 0x150 */
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PSW mcck_old_psw; /* 0x160 */
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PSW io_old_psw; /* 0x170 */
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uint8_t pad8[0x1a0 - 0x180]; /* 0x180 */
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PSW restart_new_psw; /* 0x1a0 */
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PSW external_new_psw; /* 0x1b0 */
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PSW svc_new_psw; /* 0x1c0 */
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PSW program_new_psw; /* 0x1d0 */
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PSW mcck_new_psw; /* 0x1e0 */
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PSW io_new_psw; /* 0x1f0 */
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} __attribute__((packed, aligned(8192))) LowCore;
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extern LowCore *lowcore;
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static inline void set_prefix(uint32_t address)
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{
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asm volatile("spx %0" : : "m" (address) : "memory");
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}
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static inline uint32_t store_prefix(void)
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{
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uint32_t address;
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asm volatile("stpx %0" : "=m" (address));
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return address;
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}
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#endif
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