qemu/tests/tcg/mips
Petar Jovanovic eec8972a5b target-mips: Fix incorrect reads and writes to DSPControl register
Upper 4 bits of ccond (bits 31..28 ) of DSPControl register are not used in
the MIPS32 architecture. They are used in the MIPS64 architecture. For MIPS32
these bits must be written as zero, and return zero on read.

The change fixes writes (WRDSP) and reads (RDDSP) to the register. It also fixes
the tests that use these instructions, and makes them smaller and simpler.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-01 11:10:47 +01:00
..
mips32-dsp target-mips: Fix incorrect reads and writes to DSPControl register 2013-01-01 11:10:47 +01:00
mips32-dspr2 target-mips: Add ASE DSP testcases 2012-10-31 21:37:21 +01:00
mips64-dsp target-mips: Add ASE DSP testcases 2012-10-31 21:37:21 +01:00
mips64-dspr2 target-mips: Add ASE DSP testcases 2012-10-31 21:37:21 +01:00