d780d056f8
The ARM_CPU_IRQ/FIQ definitions are used to index the GPIO IRQ created calling qdev_init_gpio_in() in ARMCPU instance_init() handler. To allow non-ARM code to raise interrupt on ARM cores, move they to 'target/arm/cpu-qom.h' which is non-ARM specific and can be included by any hw/ file. File list to include the new header generated using: $ git grep -wEl 'ARM_CPU_(\w*IRQ|FIQ)' Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-18-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
/*
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* QEMU ARM CPU QOM header (target agnostic)
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#ifndef QEMU_ARM_CPU_QOM_H
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#define QEMU_ARM_CPU_QOM_H
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#include "hw/core/cpu.h"
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#define TYPE_ARM_CPU "arm-cpu"
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OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
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#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
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#define TYPE_AARCH64_CPU "aarch64-cpu"
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typedef struct AArch64CPUClass AArch64CPUClass;
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DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
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TYPE_AARCH64_CPU)
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#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
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#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
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/* Meanings of the ARMCPU object's four inbound GPIO lines */
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#define ARM_CPU_IRQ 0
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#define ARM_CPU_FIQ 1
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#define ARM_CPU_VIRQ 2
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#define ARM_CPU_VFIQ 3
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/* For M profile, some registers are banked secure vs non-secure;
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* these are represented as a 2-element array where the first element
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* is the non-secure copy and the second is the secure copy.
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* When the CPU does not have implement the security extension then
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* only the first element is used.
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* This means that the copy for the current security state can be
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* accessed via env->registerfield[env->v7m.secure] (whether the security
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* extension is implemented or not).
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*/
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enum {
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M_REG_NS = 0,
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M_REG_S = 1,
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M_REG_NUM_BANKS = 2,
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};
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#endif
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