Alistair Francis ed6eebaaaf target/riscv: Add ePMP support for the Ibex CPU ...

The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com

2021-05-11 20:02:06 +10:00

..

insn_trans

riscv: Add semihosting support

2021-01-18 10:05:06 +00:00

arch_dump.c

target-riscv: support QMP dump-guest-memory

2021-03-04 09:43:29 -05:00

cpu_bits.h

target/riscv: Define ePMP mseccfg

2021-05-11 20:02:06 +10:00

cpu_helper.c

riscv: don't look at SUM when accessing memory from a debugger context

2021-05-11 20:02:06 +10:00

cpu_user.h

…

cpu-param.h

target/riscv: Add a virtualised MMU Mode

2020-11-09 15:08:45 -08:00

cpu.c

target/riscv: Add ePMP support for the Ibex CPU

2021-05-11 20:02:06 +10:00

cpu.h

target/riscv: Add a config option for ePMP

2021-05-11 20:02:06 +10:00

csr.c

target/riscv: Add ePMP CSR access functions

2021-05-11 20:02:06 +10:00

fpu_helper.c

target/riscv: fpu_helper: Match function defs in HELPER macros

2020-12-17 21:56:44 -08:00

gdbstub.c

target/riscv: Use RISCVException enum for CSR access

2021-05-11 20:02:06 +10:00

helper.h

target/riscv: fpu_helper: Match function defs in HELPER macros

2020-12-17 21:56:44 -08:00

insn16-32.decode

…

insn16-64.decode

…

insn16.decode

…

insn32-64.decode

…

insn32.decode

…

instmap.h

…

internals.h

target/riscv: Add basic vmstate description of CPU

2020-11-03 07:17:23 -08:00

machine.c

target/riscv: Remove privilege v1.9 specific CSR related code

2021-05-11 20:01:10 +10:00

meson.build

target-riscv: support QMP dump-guest-memory

2021-03-04 09:43:29 -05:00

monitor.c

hmp: Pass monitor to mon_get_cpu_env()

2020-11-13 12:45:51 +00:00

op_helper.c

target/riscv: Use RISCVException enum for CSR access

2021-05-11 20:02:06 +10:00

pmp.c

target/riscv/pmp: Remove outdated comment

2021-05-11 20:02:06 +10:00

pmp.h

target/riscv: Add ePMP CSR access functions

2021-05-11 20:02:06 +10:00

trace-events

target/riscv: Add ePMP CSR access functions

2021-05-11 20:02:06 +10:00

trace.h

…

translate.c

target/riscv: Remove privilege v1.9 specific CSR related code

2021-05-11 20:01:10 +10:00

vector_helper.c

target/riscv: Fixup saturate subtract function

2021-05-11 20:02:06 +10:00