Alistair Francis ed5abf46b3

target/riscv: Correctly implement TSR trap ...

As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.

This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jonathan Behrens <jonathan@fintelia.io
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

2020-03-16 17:03:13 -07:00

..

insn_trans

target/riscv: Remove the hret instruction

2020-02-27 13:45:45 -08:00

cpu_bits.h

target/riscv: Add the MSTATUS_MPV_ISSET helper macro

2020-02-27 13:46:33 -08:00

cpu_helper.c

target/riscv: Emulate TIME CSRs for privileged mode

2020-02-27 13:46:36 -08:00

cpu_user.h

…

cpu-param.h

…

cpu.c

RISC-V: Add a missing "," in riscv_excp_names

2020-03-05 12:01:43 -08:00

cpu.h

target/riscv: Emulate TIME CSRs for privileged mode

2020-02-27 13:46:36 -08:00

csr.c

target/riscv: Emulate TIME CSRs for privileged mode

2020-02-27 13:46:36 -08:00

fpu_helper.c

…

gdbstub.c

target/riscv: Add the Hypervisor CSRs to CPUState

2020-02-27 13:45:25 -08:00

helper.h

…

insn16-32.decode

…

insn16-64.decode

…

insn16.decode

…

insn32-64.decode

…

insn32.decode

target/riscv: Remove the hret instruction

2020-02-27 13:45:45 -08:00

instmap.h

target/riscv: progressively load the instruction during decode

2020-02-25 20:20:23 +00:00

Makefile.objs

…

monitor.c

…

op_helper.c

target/riscv: Correctly implement TSR trap

2020-03-16 17:03:13 -07:00

pmp.c

…

pmp.h

…

trace-events

…

translate.c

target/riscv: Add the MSTATUS_MPV_ISSET helper macro

2020-02-27 13:46:33 -08:00