qemu/target
Max Filippov ed07f685ad target/xtensa: support copying registers up to 64 bits wide
FLIX dependency breaking code assumes that all registers are 32 bit
wide. This may not always be correct.
Extract actual register width from the associated register file and use
it to create temporaries of correct width and generate correct data
movement instructions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21 12:48:15 -07:00
..
alpha meson: target 2020-08-21 06:30:35 -04:00
arm meson: target 2020-08-21 06:30:35 -04:00
avr meson: target 2020-08-21 06:30:35 -04:00
cris meson: target 2020-08-21 06:30:35 -04:00
hppa meson: target 2020-08-21 06:30:35 -04:00
i386 meson: target 2020-08-21 06:30:35 -04:00
lm32 meson: target 2020-08-21 06:30:35 -04:00
m68k meson: target 2020-08-21 06:30:35 -04:00
microblaze meson: target 2020-08-21 06:30:35 -04:00
mips meson: target 2020-08-21 06:30:35 -04:00
moxie meson: target 2020-08-21 06:30:35 -04:00
nios2 meson: target 2020-08-21 06:30:35 -04:00
openrisc meson: target 2020-08-21 06:30:35 -04:00
ppc meson: target 2020-08-21 06:30:35 -04:00
riscv meson: target 2020-08-21 06:30:35 -04:00
rx meson: target 2020-08-21 06:30:35 -04:00
s390x meson: link emulators without Makefile.target 2020-08-21 06:30:40 -04:00
sh4 meson: target 2020-08-21 06:30:35 -04:00
sparc meson: target 2020-08-21 06:30:35 -04:00
tilegx meson: target 2020-08-21 06:30:35 -04:00
tricore meson: target 2020-08-21 06:30:35 -04:00
unicore32 meson: target 2020-08-21 06:30:35 -04:00
xtensa target/xtensa: support copying registers up to 64 bits wide 2020-08-21 12:48:15 -07:00
meson.build meson: target 2020-08-21 06:30:35 -04:00