Filip Bozuta 2c5bf8108e target/mips: Refactor handling of vector compare 'less than' (signed) instructions ...

Remove unnecessary argument and provide separate function for each
instruction.

Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1571837825-24438-3-git-send-email-Filip.Bozuta@rt-rk.com>

2019-10-25 18:37:01 +02:00

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alpha

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arm

target/arm: Rely on hflags correct in cpu_get_tb_cpu_state

2019-10-24 17:16:28 +01:00

cris

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hppa

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i386

target/i386: Introduce Denverton CPU model

2019-10-23 23:37:42 -03:00

lm32

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m68k

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microblaze

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mips

target/mips: Refactor handling of vector compare 'less than' (signed) instructions

2019-10-25 18:37:01 +02:00

moxie

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nios2

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openrisc

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ppc

target/ppc: Fix for optimized vsl/vsr instructions

2019-10-24 09:36:55 +11:00

riscv

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s390x

s390x/kvm: Set default cpu model for all machine classes

2019-10-21 18:03:08 +02:00

sh4

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sparc

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tilegx

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tricore

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unicore32

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xtensa

target/xtensa: regenerate and re-import test_mmuhifi_c3 core

2019-10-18 19:54:27 -07:00