afd46fcad2
In icount mode, instructions that access io memory spaces in the middle
of the translation block invoke TB recompilation. After recompilation,
such instructions become last in the TB and are allowed to access io
memory spaces.
When the code includes instruction like i386 'xchg eax, 0xffffd080'
which accesses APIC, QEMU goes into an infinite loop of the recompilation.
This instruction includes two memory accesses - one read and one write.
After the first access, APIC calls cpu_report_tpr_access, which restores
the CPU state to get the current eip. But cpu_restore_state_from_tb
resets the cpu->can_do_io flag which makes the second memory access invalid.
Therefore the second memory access causes a recompilation of the block.
Then these operations repeat again and again.
This patch moves resetting cpu->can_do_io flag from
cpu_restore_state_from_tb to cpu_loop_exit* functions.
It also adds a parameter for cpu_restore_state which controls restoring
icount. There is no need to restore icount when we only query CPU state
without breaking the TB. Restoring it in such cases leads to the
incorrect flow of the virtual time.
In most cases new parameter is true (icount should be recalculated).
But there are two cases in i386 and openrisc when the CPU state is only
queried without the need to break the TB. This patch fixes both of
these cases.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
Message-Id: <20180409091320.12504.35329.stgit@pasha-VirtualBox>
[rth: Make can_do_io setting unconditional; move from cpu_exec;
make cpu_loop_exit_{noexc,restore} call cpu_loop_exit.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
325 lines
9.9 KiB
C
325 lines
9.9 KiB
C
/*
|
|
* OpenRISC system instructions helper routines
|
|
*
|
|
* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
|
|
* Zhizhou Zhang <etouzh@gmail.com>
|
|
*
|
|
* This library is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
* License as published by the Free Software Foundation; either
|
|
* version 2 of the License, or (at your option) any later version.
|
|
*
|
|
* This library is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* Lesser General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#include "qemu/osdep.h"
|
|
#include "cpu.h"
|
|
#include "exec/exec-all.h"
|
|
#include "exec/helper-proto.h"
|
|
#include "exception.h"
|
|
#include "sysemu/sysemu.h"
|
|
|
|
#define TO_SPR(group, number) (((group) << 11) + (number))
|
|
|
|
void HELPER(mtspr)(CPUOpenRISCState *env,
|
|
target_ulong ra, target_ulong rb, target_ulong offset)
|
|
{
|
|
#ifndef CONFIG_USER_ONLY
|
|
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
|
|
CPUState *cs = CPU(cpu);
|
|
int spr = (ra | offset);
|
|
int idx;
|
|
|
|
switch (spr) {
|
|
case TO_SPR(0, 0): /* VR */
|
|
env->vr = rb;
|
|
break;
|
|
|
|
case TO_SPR(0, 11): /* EVBAR */
|
|
env->evbar = rb;
|
|
break;
|
|
|
|
case TO_SPR(0, 16): /* NPC */
|
|
cpu_restore_state(cs, GETPC(), true);
|
|
/* ??? Mirror or1ksim in not trashing delayed branch state
|
|
when "jumping" to the current instruction. */
|
|
if (env->pc != rb) {
|
|
env->pc = rb;
|
|
env->dflag = 0;
|
|
cpu_loop_exit(cs);
|
|
}
|
|
break;
|
|
|
|
case TO_SPR(0, 17): /* SR */
|
|
if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
|
|
(rb & (SR_IME | SR_DME | SR_SM))) {
|
|
tlb_flush(cs);
|
|
}
|
|
cpu_set_sr(env, rb);
|
|
if (env->sr & SR_DME) {
|
|
env->tlb->cpu_openrisc_map_address_data =
|
|
&cpu_openrisc_get_phys_data;
|
|
} else {
|
|
env->tlb->cpu_openrisc_map_address_data =
|
|
&cpu_openrisc_get_phys_nommu;
|
|
}
|
|
|
|
if (env->sr & SR_IME) {
|
|
env->tlb->cpu_openrisc_map_address_code =
|
|
&cpu_openrisc_get_phys_code;
|
|
} else {
|
|
env->tlb->cpu_openrisc_map_address_code =
|
|
&cpu_openrisc_get_phys_nommu;
|
|
}
|
|
break;
|
|
|
|
case TO_SPR(0, 18): /* PPC */
|
|
env->ppc = rb;
|
|
break;
|
|
|
|
case TO_SPR(0, 32): /* EPCR */
|
|
env->epcr = rb;
|
|
break;
|
|
|
|
case TO_SPR(0, 48): /* EEAR */
|
|
env->eear = rb;
|
|
break;
|
|
|
|
case TO_SPR(0, 64): /* ESR */
|
|
env->esr = rb;
|
|
break;
|
|
|
|
case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
|
|
idx = (spr - 1024);
|
|
env->shadow_gpr[idx / 32][idx % 32] = rb;
|
|
|
|
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
|
|
idx = spr - TO_SPR(1, 512);
|
|
if (!(rb & 1)) {
|
|
tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
|
|
}
|
|
env->tlb->dtlb[0][idx].mr = rb;
|
|
break;
|
|
|
|
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
|
|
idx = spr - TO_SPR(1, 640);
|
|
env->tlb->dtlb[0][idx].tr = rb;
|
|
break;
|
|
case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
|
|
case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
|
|
case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
|
|
case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
|
|
case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
|
|
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
|
|
break;
|
|
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
|
|
idx = spr - TO_SPR(2, 512);
|
|
if (!(rb & 1)) {
|
|
tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
|
|
}
|
|
env->tlb->itlb[0][idx].mr = rb;
|
|
break;
|
|
|
|
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
|
|
idx = spr - TO_SPR(2, 640);
|
|
env->tlb->itlb[0][idx].tr = rb;
|
|
break;
|
|
case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
|
|
case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
|
|
case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
|
|
case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
|
|
case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
|
|
case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
|
|
break;
|
|
case TO_SPR(5, 1): /* MACLO */
|
|
env->mac = deposit64(env->mac, 0, 32, rb);
|
|
break;
|
|
case TO_SPR(5, 2): /* MACHI */
|
|
env->mac = deposit64(env->mac, 32, 32, rb);
|
|
break;
|
|
case TO_SPR(8, 0): /* PMR */
|
|
env->pmr = rb;
|
|
if (env->pmr & PMR_DME || env->pmr & PMR_SME) {
|
|
cpu_restore_state(cs, GETPC(), true);
|
|
env->pc += 4;
|
|
cs->halted = 1;
|
|
raise_exception(cpu, EXCP_HALTED);
|
|
}
|
|
break;
|
|
case TO_SPR(9, 0): /* PICMR */
|
|
env->picmr |= rb;
|
|
break;
|
|
case TO_SPR(9, 2): /* PICSR */
|
|
env->picsr &= ~rb;
|
|
break;
|
|
case TO_SPR(10, 0): /* TTMR */
|
|
{
|
|
if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
|
|
switch (rb & TTMR_M) {
|
|
case TIMER_NONE:
|
|
cpu_openrisc_count_stop(cpu);
|
|
break;
|
|
case TIMER_INTR:
|
|
case TIMER_SHOT:
|
|
case TIMER_CONT:
|
|
cpu_openrisc_count_start(cpu);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
int ip = env->ttmr & TTMR_IP;
|
|
|
|
if (rb & TTMR_IP) { /* Keep IP bit. */
|
|
env->ttmr = (rb & ~TTMR_IP) | ip;
|
|
} else { /* Clear IP bit. */
|
|
env->ttmr = rb & ~TTMR_IP;
|
|
cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
|
|
}
|
|
|
|
cpu_openrisc_timer_update(cpu);
|
|
}
|
|
break;
|
|
|
|
case TO_SPR(10, 1): /* TTCR */
|
|
cpu_openrisc_count_set(cpu, rb);
|
|
if (env->ttmr & TIMER_NONE) {
|
|
return;
|
|
}
|
|
cpu_openrisc_timer_update(cpu);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
|
|
target_ulong rd, target_ulong ra, uint32_t offset)
|
|
{
|
|
#ifndef CONFIG_USER_ONLY
|
|
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
|
|
CPUState *cs = CPU(cpu);
|
|
int spr = (ra | offset);
|
|
int idx;
|
|
|
|
switch (spr) {
|
|
case TO_SPR(0, 0): /* VR */
|
|
return env->vr & SPR_VR;
|
|
|
|
case TO_SPR(0, 1): /* UPR */
|
|
return env->upr; /* TT, DM, IM, UP present */
|
|
|
|
case TO_SPR(0, 2): /* CPUCFGR */
|
|
return env->cpucfgr;
|
|
|
|
case TO_SPR(0, 3): /* DMMUCFGR */
|
|
return env->dmmucfgr; /* 1Way, 64 entries */
|
|
|
|
case TO_SPR(0, 4): /* IMMUCFGR */
|
|
return env->immucfgr;
|
|
|
|
case TO_SPR(0, 11): /* EVBAR */
|
|
return env->evbar;
|
|
|
|
case TO_SPR(0, 16): /* NPC (equals PC) */
|
|
cpu_restore_state(cs, GETPC(), false);
|
|
return env->pc;
|
|
|
|
case TO_SPR(0, 17): /* SR */
|
|
return cpu_get_sr(env);
|
|
|
|
case TO_SPR(0, 18): /* PPC */
|
|
cpu_restore_state(cs, GETPC(), false);
|
|
return env->ppc;
|
|
|
|
case TO_SPR(0, 32): /* EPCR */
|
|
return env->epcr;
|
|
|
|
case TO_SPR(0, 48): /* EEAR */
|
|
return env->eear;
|
|
|
|
case TO_SPR(0, 64): /* ESR */
|
|
return env->esr;
|
|
|
|
case TO_SPR(0, 128): /* COREID */
|
|
return cpu->parent_obj.cpu_index;
|
|
|
|
case TO_SPR(0, 129): /* NUMCORES */
|
|
return max_cpus;
|
|
|
|
case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
|
|
idx = (spr - 1024);
|
|
return env->shadow_gpr[idx / 32][idx % 32];
|
|
|
|
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
|
|
idx = spr - TO_SPR(1, 512);
|
|
return env->tlb->dtlb[0][idx].mr;
|
|
|
|
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
|
|
idx = spr - TO_SPR(1, 640);
|
|
return env->tlb->dtlb[0][idx].tr;
|
|
|
|
case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
|
|
case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
|
|
case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
|
|
case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
|
|
case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
|
|
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
|
|
break;
|
|
|
|
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
|
|
idx = spr - TO_SPR(2, 512);
|
|
return env->tlb->itlb[0][idx].mr;
|
|
|
|
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
|
|
idx = spr - TO_SPR(2, 640);
|
|
return env->tlb->itlb[0][idx].tr;
|
|
|
|
case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
|
|
case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
|
|
case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
|
|
case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
|
|
case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
|
|
case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
|
|
break;
|
|
|
|
case TO_SPR(5, 1): /* MACLO */
|
|
return (uint32_t)env->mac;
|
|
break;
|
|
case TO_SPR(5, 2): /* MACHI */
|
|
return env->mac >> 32;
|
|
break;
|
|
|
|
case TO_SPR(8, 0): /* PMR */
|
|
return env->pmr;
|
|
|
|
case TO_SPR(9, 0): /* PICMR */
|
|
return env->picmr;
|
|
|
|
case TO_SPR(9, 2): /* PICSR */
|
|
return env->picsr;
|
|
|
|
case TO_SPR(10, 0): /* TTMR */
|
|
return env->ttmr;
|
|
|
|
case TO_SPR(10, 1): /* TTCR */
|
|
cpu_openrisc_count_update(cpu);
|
|
return cpu_openrisc_count_get(cpu);
|
|
|
|
default:
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
/* for rd is passed in, if rd unchanged, just keep it back. */
|
|
return rd;
|
|
}
|