Daniel Henrique Barboza ec34cd732c target/riscv/cpu.c: mark extensions arrays as 'const' ... We'll need to export these arrays to the accelerator classes in the next patches. Mark them as 'const' now because they should not be modified at runtime. Note that 'riscv_cpu_options' will also be exported, but can't be marked as 'const', because the properties are changed via qdev_property_add_static(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-10-12 12:02:17 +10:00
..
insn_trans	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
tcg	target/riscv: move riscv_tcg_ops to tcg-cpu.c	2023-10-12 11:59:03 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Update CSR bits name for svadu extension	2023-09-11 11:45:55 +10:00
cpu_cfg.h	target/riscv: Add Zihintntl extension ISA string to DTS	2023-09-11 11:45:55 +10:00
cpu_helper.c	target/riscv: Update CSR bits name for svadu extension	2023-09-11 11:45:55 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h	target/riscv: add 'max' CPU type	2023-10-12 11:39:33 +10:00
cpu.c	target/riscv/cpu.c: mark extensions arrays as 'const'	2023-10-12 12:02:17 +10:00
cpu.h	target/riscv: move riscv_tcg_ops to tcg-cpu.c	2023-10-12 11:59:03 +10:00
crypto_helper.c	target/riscv: Use accelerated helper for AES64KS1I	2023-09-11 11:45:55 +10:00
csr.c	target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c	2023-10-12 11:57:46 +10:00
debug.c	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
debug.h	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
fpu_helper.c	riscv: Add support for the Zfa extension	2023-07-10 22:29:20 +10:00
gdbstub.c
helper.h	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
insn16.decode
insn32.decode	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
instmap.h
internals.h
Kconfig
kvm_riscv.h	target/riscv: Clear CSR values at reset and sync MPSTATE with host	2023-10-12 11:52:43 +10:00
kvm-stub.c
kvm.c	target/riscv: move 'host' CPU declaration to kvm.c	2023-10-12 12:01:10 +10:00
m128_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
machine.c
meson.build	target/riscv: introduce TCG AccelCPUClass	2023-10-12 11:55:21 +10:00
monitor.c	riscv: spelling fixes	2023-09-08 13:08:52 +03:00
op_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
pmp.c	target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes	2023-09-11 11:45:55 +10:00
pmp.h
pmu.c	target/riscv/pmu: Restrict 'qemu/log.h' include to source	2023-08-31 19:47:43 +02:00
pmu.h	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
riscv-qmp-cmds.c
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	accel/tcg: Replace CPUState.env_ptr with cpu_env()	2023-10-04 11:03:54 -07:00
vcrypto_helper.c	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
vector_helper.c	tcg: Correct invalid mentions of 'softmmu' by 'system-mode'	2023-10-07 19:02:33 +02:00
vector_internals.c	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:54 +10:00
vector_internals.h	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:55 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c