e92dd33224
accel/tcg/ files requires the following definitions: - TARGET_LONG_BITS - TARGET_PAGE_BITS - TARGET_PHYS_ADDR_SPACE_BITS - TCG_GUEST_DEFAULT_MO The first 3 are defined in "cpu-param.h". The last one in "cpu.h", with a bunch of definitions irrelevant for TCG. By moving the TCG_GUEST_DEFAULT_MO definition to "cpu-param.h", we can simplify various accel/tcg includes. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20231211212003.21686-4-philmd@linaro.org>
33 lines
913 B
C
33 lines
913 B
C
/*
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* PA-RISC cpu parameters for qemu.
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*
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* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
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* SPDX-License-Identifier: LGPL-2.0+
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*/
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#ifndef HPPA_CPU_PARAM_H
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#define HPPA_CPU_PARAM_H
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#define TARGET_LONG_BITS 64
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#if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32)
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# define TARGET_PHYS_ADDR_SPACE_BITS 32
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#else
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/* ??? PA-8000 through 8600 have 40 bits; PA-8700 and 8900 have 44 bits. */
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# define TARGET_PHYS_ADDR_SPACE_BITS 40
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# define TARGET_VIRT_ADDR_SPACE_BITS 64
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#endif
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#define TARGET_PAGE_BITS 12
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/* PA-RISC 1.x processors have a strong memory model. */
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/*
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* ??? While we do not yet implement PA-RISC 2.0, those processors have
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* a weak memory model, but with TLB bits that force ordering on a per-page
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* basis. It's probably easier to fall back to a strong memory model.
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*/
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#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
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#endif
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