Daniel Henrique Barboza cc2bf69a36 target/riscv: add zicbop extension flag ... QEMU already implements zicbom (Cache Block Management Operations) and zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for what would be the instructions for zicbop (Cache Block Prefetch Operations), which are now no-ops. The RVA22U64 profile mandates zicbop, which means that applications that run with this profile might expect zicbop to be present in the riscv,isa DT and might behave badly if it's absent. Adding zicbop as an extension will make our future RVA22U64 implementation more in line with what userspace expects and, if/when cache block prefetch operations became relevant to QEMU, we already have the extension flag to turn then on/off as needed. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231218125334.37184-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-01-10 18:47:47 +10:00
..
boot.c	target/riscv: rename ext_icsr to ext_zicsr	2023-11-07 11:02:17 +10:00
Kconfig	hw/riscv/virt-acpi-build.c: Add IO controllers and devices	2024-01-10 18:47:47 +10:00
meson.build
microchip_pfsoc.c	riscv: spelling fixes	2023-09-08 13:08:52 +03:00
numa.c	hw/riscv: Fix typo field in error_report	2023-07-19 14:31:41 +10:00
opentitan.c	hw/riscv: opentitan: Fixup local variables shadowing	2023-09-29 10:07:20 +02:00
riscv_hart.c
shakti_c.c	hw/riscv/shakti_c: Check CPU type in machine_run_board_init()	2024-01-05 16:20:15 +01:00
sifive_e.c	riscv: Fix SiFive E CLINT clock frequency	2023-11-22 13:57:19 +10:00
sifive_u.c	hw/sd: Introduce a "sd-card" SPI variant model	2023-09-01 11:40:04 +02:00
spike.c
virt-acpi-build.c	hw/riscv/virt-acpi-build.c: Add PLIC in MADT	2024-01-10 18:47:47 +10:00
virt.c	target/riscv: add zicbop extension flag	2024-01-10 18:47:47 +10:00