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Peter Maydell ea72ac9bc8 target-arm queue: 
* target/arm: Fix some bugs in secure EL2 handling
  * target/arm: Fix assert when !HAVE_CMPXCHG128
  * MAINTAINERS: change Fred Konrad's email address
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Merge tag 'pull-target-arm-20220401' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * target/arm: Fix some bugs in secure EL2 handling
 * target/arm: Fix assert when !HAVE_CMPXCHG128
 * MAINTAINERS: change Fred Konrad's email address

# gpg: Signature made Fri 01 Apr 2022 15:59:59 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20220401' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen
  MAINTAINERS: change Fred Konrad's email address
  target/arm: Determine final stage 2 output PA space based on original IPA
  target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk
  target/arm: Check VSTCR.SW when assigning the stage 2 output PA space
  target/arm: Fix MTE access checks for disabled SEL2

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-04-01 17:16:48 +01:00
..
alpha target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
arm target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen 2022-04-01 15:35:49 +01:00
avr target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
cris target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
hexagon target/hexagon: remove unused variable 2022-03-12 09:14:22 -08:00
hppa target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
i386 Bugfixes. 2022-03-25 10:14:47 +00:00
m68k m68k/nios2-semi: fix gettimeofday() result check 2022-03-22 14:39:06 +04:00
microblaze target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
mips target/mips: Fix address space range declaration on n32 2022-03-29 00:51:50 +02:00
nios2 m68k/nios2-semi: fix gettimeofday() result check 2022-03-22 14:39:06 +04:00
openrisc target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
ppc target/ppc: fix helper_xvmadd* argument order 2022-03-26 13:52:37 +01:00
riscv target/riscv: rvv: Add missing early exit condition for whole register load/store 2022-04-01 08:40:55 +10:00
rx target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
s390x Use g_new() & friends where that makes obvious sense 2022-03-21 15:44:44 +01:00
sh4 target/sh4: Remove old README.sh4 file 2022-03-31 21:29:15 +02:00
sparc target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
tricore target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
xtensa target: Use ArchCPU as interface to target CPU 2022-03-06 22:23:09 +01:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00