qemu/target-arm
Fabian Aggeler ea30a4b824 target-arm: add banked register accessors
If EL3 is in AArch32 state certain cp registers are banked (secure and
non-secure instance). When reading or writing to coprocessor registers
the following macros can be used.

- A32_BANKED macros are used for choosing the banked register based on provided
  input security argument.  This macro is used to choose the bank during
  translation of MRC/MCR instructions that are dependent on something other
  than the current secure state.
- A32_BANKED_CURRENT macros are used for choosing the banked register based on
  current secure state.  This is NOT to be used for choosing the bank used
  during translation as it breaks monitor mode.

If EL3 is operating in AArch64 state coprocessor registers are not
banked anymore. The macros use the non-secure instance (_ns) in this
case, which is architecturally mapped to the AArch64 EL register.

Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-4-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11 12:07:48 +00:00
..
Makefile.objs target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
arm-semi.c Pass semihosting exit code back to system. 2014-12-11 12:07:48 +00:00
arm_ldst.h softmmu: introduce cpu_ldst.h 2014-06-05 16:10:33 +02:00
cpu-qom.h target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
cpu.c target-arm: Separate out M profile cpu_exec_interrupt handling 2014-11-04 12:05:23 +00:00
cpu.h target-arm: add banked register accessors 2014-12-11 12:07:48 +00:00
cpu64.c target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" 2014-10-24 12:19:13 +01:00
crypto_helper.c target-arm: Use Common Tables in AES Instructions 2014-06-16 13:24:33 +02:00
gdbstub.c
gdbstub64.c
helper-a64.c target-arm: rename arm_current_pl to arm_current_el 2014-10-24 12:19:14 +01:00
helper-a64.h target-arm: A64: Implement CRC instructions 2014-06-09 16:06:12 +01:00
helper.c target-arm: add async excp target_el function 2014-12-11 12:07:48 +00:00
helper.h target-arm: A64: Emulate the SMC insn 2014-09-29 18:48:50 +01:00
internals.h target-arm: rename arm_current_pl to arm_current_el 2014-10-24 12:19:14 +01:00
iwmmxt_helper.c target-arm: Delete unused iwmmxt_msadb helper 2014-06-09 16:06:12 +01:00
kvm-consts.h target-arm: add missing PSCI constants needed for PSCI emulation 2014-10-24 12:19:12 +01:00
kvm-stub.c
kvm.c target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 2014-06-19 18:33:02 +01:00
kvm32.c target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUs 2014-07-08 13:05:11 +01:00
kvm64.c target-arm: A64: Break out aarch64_save/restore_sp 2014-08-04 14:41:54 +01:00
kvm_arm.h target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 2014-06-19 18:33:02 +01:00
machine.c target-arm: increase arrays of registers R13 & R14 2014-10-24 12:19:14 +01:00
neon_helper.c target-arm: add support for v8 VMULL.P64 instruction 2014-06-09 16:06:11 +01:00
op_addsub.h
op_helper.c target-arm: A32: Emulate the SMC instruction 2014-10-24 12:19:15 +01:00
psci.c target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
translate-a64.c target-arm: A64: remove redundant store 2014-11-02 10:04:34 +03:00
translate.c target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn() 2014-11-04 12:05:11 +00:00
translate.h target-arm: rename arm_current_pl to arm_current_el 2014-10-24 12:19:14 +01:00