c696e1f2b3
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible controller. The SDHCI compatible registers start from offset 0x200, which are called Slot Register Set (SRS) in its datasheet. This creates a Cadence SDHCI model built on top of the existing generic SDHCI model. Cadence specific Host Register Set (HRS) is implemented to make guest software happy. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
/*
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* Cadence SDHCI emulation
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CADENCE_SDHCI_H
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#define CADENCE_SDHCI_H
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#include "hw/sd/sdhci.h"
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#define CADENCE_SDHCI_REG_SIZE 0x100
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#define CADENCE_SDHCI_NUM_REGS (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t))
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typedef struct CadenceSDHCIState {
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SysBusDevice parent;
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MemoryRegion container;
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MemoryRegion iomem;
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BusState *bus;
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uint32_t regs[CADENCE_SDHCI_NUM_REGS];
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SDHCIState sdhci;
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} CadenceSDHCIState;
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#define TYPE_CADENCE_SDHCI "cadence.sdhci"
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#define CADENCE_SDHCI(obj) OBJECT_CHECK(CadenceSDHCIState, (obj), \
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TYPE_CADENCE_SDHCI)
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#endif /* CADENCE_SDHCI_H */
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