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Weiwei Li e9a7ef5d5e target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension 
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions

Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-10-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29 10:47:45 +10:00
..
insn_trans
target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
2022-04-29 10:47:45 +10:00
arch_dump.c
…
bitmanip_helper.c
target/riscv: rvk: add support for zbkx extension
2022-04-29 10:47:45 +10:00
cpu_bits.h
target/riscv: Add *envcfg* CSRs support
2022-04-22 10:35:16 +10:00
cpu_helper.c
hw/intc: Make RISC-V ACLINT mtime MMIO register writable
2022-04-22 10:35:16 +10:00
cpu_user.h
…
cpu-param.h
…
cpu.c
target/riscv: rvk: add cfg properties for zbk* and zk*
2022-04-29 10:47:45 +10:00
cpu.h
target/riscv: rvk: add cfg properties for zbk* and zk*
2022-04-29 10:47:45 +10:00
crypto_helper.c
target/riscv: rvk: add support for zkne/zknd extension in RV64
2022-04-29 10:47:45 +10:00
csr.c
target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
2022-04-29 10:47:45 +10:00
debug.c
target/riscv: csr: Hook debug CSR read/write
2022-04-22 10:35:16 +10:00
debug.h
target/riscv: csr: Hook debug CSR read/write
2022-04-22 10:35:16 +10:00
fpu_helper.c
target/riscv: add support for zhinx/zhinxmin
2022-03-03 13:14:50 +10:00
gdbstub.c
target/riscv: correct "code should not be reached" for x-rv128
2022-02-16 12:24:18 +10:00
helper.h
target/riscv: rvk: add support for zkne/zknd extension in RV64
2022-04-29 10:47:45 +10:00
insn16.decode
target/riscv: accessors to registers upper part and 128-bit load/store
2022-01-08 15:46:10 +10:00
insn32.decode
target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
2022-04-29 10:47:45 +10:00
instmap.h
…
internals.h
target/riscv: add support for zhinx/zhinxmin
2022-03-03 13:14:50 +10:00
Kconfig
…
kvm_riscv.h
target/riscv: Support setting external interrupt by KVM
2022-01-21 15:52:56 +10:00
kvm-stub.c
target/riscv: Support setting external interrupt by KVM
2022-01-21 15:52:56 +10:00
kvm.c
Remove qemu-common.h include from most units
2022-04-06 14:31:55 +02:00
m128_helper.c
target/riscv: support for 128-bit M extension
2022-01-08 15:46:10 +10:00
machine.c
target/riscv: machine: Add debug state description
2022-04-22 10:35:16 +10:00
meson.build
target/riscv: rvk: add support for zknd/zkne extension in RV32
2022-04-29 10:47:45 +10:00
monitor.c
…
op_helper.c
compiler.h: replace QEMU_NORETURN with G_NORETURN
2022-04-21 17:03:51 +04:00
pmp.c
target/riscv/pmp: fix NAPOT range computation overflow
2022-04-22 10:35:16 +10:00
pmp.h
target: Include missing 'cpu.h'
2022-03-06 13:15:42 +01:00
sbi_ecall_interface.h
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
2022-01-21 15:52:56 +10:00
trace-events
…
trace.h
…
translate.c
target/riscv: rvk: add support for zknd/zkne extension in RV32
2022-04-29 10:47:45 +10:00
vector_helper.c
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
2022-04-22 10:35:16 +10:00
XVentanaCondOps.decode
target/riscv: Add XVentanaCondOps custom extension
2022-02-16 12:24:18 +10:00