e93abc147f
TCG doesn't support VMX, and nested VMX is not enabled by default in the KVM kernel module. So, there's no reason to have VMX enabled by default on the core2duo and coreduo CPU models, today. Even the newer Intel CPU model definitions don't have it enabled. In this case, we need machine-type compat code, as people may be running the older machine-types on hosts that had VMX nesting enabled. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
463 lines
14 KiB
C
463 lines
14 KiB
C
/*
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* Q35 chipset based pc system emulator
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2009, 2010
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* Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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* This is based on pc.c, but heavily modified.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h"
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#include "hw/loader.h"
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#include "sysemu/arch_init.h"
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#include "hw/i2c/smbus.h"
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#include "hw/boards.h"
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#include "hw/timer/mc146818rtc.h"
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#include "hw/xen/xen.h"
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#include "sysemu/kvm.h"
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#include "hw/kvm/clock.h"
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#include "hw/pci-host/q35.h"
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#include "exec/address-spaces.h"
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#include "hw/i386/ich9.h"
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#include "hw/i386/smbios.h"
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#include "hw/ide/pci.h"
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#include "hw/ide/ahci.h"
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#include "hw/usb.h"
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#include "hw/cpu/icc_bus.h"
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#include "qemu/error-report.h"
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/* ICH9 AHCI has 6 ports */
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#define MAX_SATA_PORTS 6
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static bool has_acpi_build = true;
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static bool smbios_defaults = true;
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static bool smbios_legacy_mode;
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/* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
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* host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte
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* pages in the host.
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*/
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static bool gigabyte_align = true;
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static bool has_reserved_memory = true;
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/* PC hardware initialisation */
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static void pc_q35_init(MachineState *machine)
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{
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PCMachineState *pc_machine = PC_MACHINE(machine);
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ram_addr_t below_4g_mem_size, above_4g_mem_size;
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Q35PCIHost *q35_host;
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PCIHostState *phb;
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PCIBus *host_bus;
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PCIDevice *lpc;
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BusState *idebus[MAX_SATA_PORTS];
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ISADevice *rtc_state;
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ISADevice *floppy;
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MemoryRegion *pci_memory;
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MemoryRegion *rom_memory;
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MemoryRegion *ram_memory;
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GSIState *gsi_state;
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ISABus *isa_bus;
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int pci_enabled = 1;
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qemu_irq *cpu_irq;
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qemu_irq *gsi;
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qemu_irq *i8259;
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int i;
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ICH9LPCState *ich9_lpc;
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PCIDevice *ahci;
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DeviceState *icc_bridge;
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PcGuestInfo *guest_info;
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ram_addr_t lowmem;
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DriveInfo *hd[MAX_SATA_PORTS];
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/* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
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* and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
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* also known as MMCFG).
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* If it doesn't, we need to split it in chunks below and above 4G.
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* In any case, try to make sure that guest addresses aligned at
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* 1G boundaries get mapped to host addresses aligned at 1G boundaries.
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* For old machine types, use whatever split we used historically to avoid
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* breaking migration.
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*/
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if (machine->ram_size >= 0xb0000000) {
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lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
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} else {
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lowmem = 0xb0000000;
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}
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/* Handle the machine opt max-ram-below-4g. It is basically doing
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* min(qemu limit, user limit).
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*/
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if (lowmem > pc_machine->max_ram_below_4g) {
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lowmem = pc_machine->max_ram_below_4g;
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if (machine->ram_size - lowmem > lowmem &&
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lowmem & ((1ULL << 30) - 1)) {
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error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
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") not a multiple of 1G; possible bad performance.",
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pc_machine->max_ram_below_4g);
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}
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}
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if (machine->ram_size >= lowmem) {
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above_4g_mem_size = machine->ram_size - lowmem;
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below_4g_mem_size = lowmem;
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} else {
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above_4g_mem_size = 0;
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below_4g_mem_size = machine->ram_size;
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}
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if (xen_enabled() && xen_hvm_init(&below_4g_mem_size, &above_4g_mem_size,
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&ram_memory) != 0) {
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fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
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exit(1);
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}
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icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
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object_property_add_child(qdev_get_machine(), "icc-bridge",
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OBJECT(icc_bridge), NULL);
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pc_cpus_init(machine->cpu_model, icc_bridge);
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pc_acpi_init("q35-acpi-dsdt.aml");
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kvmclock_create();
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/* pci enabled */
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if (pci_enabled) {
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pci_memory = g_new(MemoryRegion, 1);
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memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
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rom_memory = pci_memory;
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} else {
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pci_memory = NULL;
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rom_memory = get_system_memory();
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}
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guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
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guest_info->isapc_ram_fw = false;
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guest_info->has_acpi_build = has_acpi_build;
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guest_info->has_reserved_memory = has_reserved_memory;
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/* Migration was not supported in 2.0 for Q35, so do not bother
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* with this hack (see hw/i386/acpi-build.c).
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*/
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guest_info->legacy_acpi_table_size = 0;
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if (smbios_defaults) {
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MachineClass *mc = MACHINE_GET_CLASS(machine);
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/* These values are guest ABI, do not change */
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smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
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mc->name, smbios_legacy_mode);
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}
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/* allocate ram and load rom/bios */
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if (!xen_enabled()) {
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pc_memory_init(machine, get_system_memory(),
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below_4g_mem_size, above_4g_mem_size,
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rom_memory, &ram_memory, guest_info);
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}
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/* irq lines */
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gsi_state = g_malloc0(sizeof(*gsi_state));
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if (kvm_irqchip_in_kernel()) {
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kvm_pc_setup_irq_routing(pci_enabled);
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gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
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GSI_NUM_PINS);
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} else {
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gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
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}
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/* create pci host bus */
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q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
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object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
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q35_host->mch.ram_memory = ram_memory;
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q35_host->mch.pci_address_space = pci_memory;
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q35_host->mch.system_memory = get_system_memory();
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q35_host->mch.address_space_io = get_system_io();
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q35_host->mch.below_4g_mem_size = below_4g_mem_size;
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q35_host->mch.above_4g_mem_size = above_4g_mem_size;
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q35_host->mch.guest_info = guest_info;
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/* pci */
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qdev_init_nofail(DEVICE(q35_host));
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phb = PCI_HOST_BRIDGE(q35_host);
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host_bus = phb->bus;
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/* create ISA bus */
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lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
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ICH9_LPC_FUNC), true,
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TYPE_ICH9_LPC_DEVICE);
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object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
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TYPE_HOTPLUG_HANDLER,
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(Object **)&pc_machine->acpi_dev,
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object_property_allow_set_link,
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OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
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object_property_set_link(OBJECT(machine), OBJECT(lpc),
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PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
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ich9_lpc = ICH9_LPC_DEVICE(lpc);
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ich9_lpc->pic = gsi;
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ich9_lpc->ioapic = gsi_state->ioapic_irq;
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pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
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ICH9_LPC_NB_PIRQS);
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pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
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isa_bus = ich9_lpc->isa_bus;
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/*end early*/
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isa_bus_irqs(isa_bus, gsi);
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if (kvm_irqchip_in_kernel()) {
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i8259 = kvm_i8259_init(isa_bus);
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} else if (xen_enabled()) {
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i8259 = xen_interrupt_controller_init();
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} else {
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cpu_irq = pc_allocate_cpu_irq();
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i8259 = i8259_init(isa_bus, cpu_irq[0]);
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}
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for (i = 0; i < ISA_NUM_IRQS; i++) {
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gsi_state->i8259_irq[i] = i8259[i];
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}
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if (pci_enabled) {
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ioapic_init_gsi(gsi_state, "q35");
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}
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qdev_init_nofail(icc_bridge);
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pc_register_ferr_irq(gsi[13]);
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/* init basic PC hardware */
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pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy,
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!pc_machine->vmport, 0xff0104);
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/* connect pm stuff to lpc */
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ich9_lpc_pm_init(lpc);
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/* ahci and SATA device, for q35 1 ahci controller is built-in */
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ahci = pci_create_simple_multifunction(host_bus,
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PCI_DEVFN(ICH9_SATA1_DEV,
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ICH9_SATA1_FUNC),
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true, "ich9-ahci");
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idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
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idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
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g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
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ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
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ahci_ide_create_devs(ahci, hd);
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if (usb_enabled(false)) {
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/* Should we create 6 UHCI according to ich9 spec? */
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ehci_create_ich9_with_companions(host_bus, 0x1d);
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}
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/* TODO: Populate SPD eeprom data. */
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smbus_eeprom_init(ich9_smb_init(host_bus,
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PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
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0xb100),
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8, NULL, 0);
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pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order,
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floppy, idebus[0], idebus[1], rtc_state);
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/* the rest devices to which pci devfn is automatically assigned */
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pc_vga_init(isa_bus, host_bus);
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pc_nic_init(isa_bus, host_bus);
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if (pci_enabled) {
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pc_pci_device_init(host_bus);
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}
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}
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static void pc_compat_2_1(MachineState *machine)
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{
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x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0);
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x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0);
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}
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static void pc_compat_2_0(MachineState *machine)
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{
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pc_compat_2_1(machine);
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smbios_legacy_mode = true;
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has_reserved_memory = false;
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pc_set_legacy_acpi_data_size();
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}
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static void pc_compat_1_7(MachineState *machine)
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{
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pc_compat_2_0(machine);
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smbios_defaults = false;
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gigabyte_align = false;
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option_rom_has_mr = true;
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x86_cpu_compat_kvm_no_autoenable(FEAT_1_ECX, CPUID_EXT_X2APIC);
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}
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static void pc_compat_1_6(MachineState *machine)
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{
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pc_compat_1_7(machine);
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rom_file_has_mr = false;
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has_acpi_build = false;
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}
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static void pc_compat_1_5(MachineState *machine)
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{
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pc_compat_1_6(machine);
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}
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static void pc_compat_1_4(MachineState *machine)
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{
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pc_compat_1_5(machine);
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x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
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x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
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}
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static void pc_q35_init_2_1(MachineState *machine)
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{
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pc_compat_2_1(machine);
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pc_q35_init(machine);
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}
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static void pc_q35_init_2_0(MachineState *machine)
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{
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pc_compat_2_0(machine);
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pc_q35_init(machine);
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}
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static void pc_q35_init_1_7(MachineState *machine)
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{
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pc_compat_1_7(machine);
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pc_q35_init(machine);
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}
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static void pc_q35_init_1_6(MachineState *machine)
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{
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pc_compat_1_6(machine);
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pc_q35_init(machine);
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}
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static void pc_q35_init_1_5(MachineState *machine)
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{
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pc_compat_1_5(machine);
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pc_q35_init(machine);
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}
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static void pc_q35_init_1_4(MachineState *machine)
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{
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pc_compat_1_4(machine);
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pc_q35_init(machine);
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}
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#define PC_Q35_MACHINE_OPTIONS \
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PC_DEFAULT_MACHINE_OPTIONS, \
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.desc = "Standard PC (Q35 + ICH9, 2009)", \
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.hot_add_cpu = pc_hot_add_cpu, \
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.units_per_default_bus = 1
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#define PC_Q35_2_2_MACHINE_OPTIONS \
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PC_Q35_MACHINE_OPTIONS, \
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.default_machine_opts = "firmware=bios-256k.bin"
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static QEMUMachine pc_q35_machine_v2_2 = {
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PC_Q35_2_2_MACHINE_OPTIONS,
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.name = "pc-q35-2.2",
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.alias = "q35",
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.init = pc_q35_init,
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};
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#define PC_Q35_2_1_MACHINE_OPTIONS PC_Q35_2_2_MACHINE_OPTIONS
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static QEMUMachine pc_q35_machine_v2_1 = {
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PC_Q35_2_1_MACHINE_OPTIONS,
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.name = "pc-q35-2.1",
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.init = pc_q35_init_2_1,
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.compat_props = (GlobalProperty[]) {
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PC_COMPAT_2_1,
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{ /* end of list */ }
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},
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};
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#define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS
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static QEMUMachine pc_q35_machine_v2_0 = {
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PC_Q35_2_0_MACHINE_OPTIONS,
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.name = "pc-q35-2.0",
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.init = pc_q35_init_2_0,
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.compat_props = (GlobalProperty[]) {
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PC_COMPAT_2_0,
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{ /* end of list */ }
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},
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};
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#define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
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static QEMUMachine pc_q35_machine_v1_7 = {
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PC_Q35_1_7_MACHINE_OPTIONS,
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.name = "pc-q35-1.7",
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.init = pc_q35_init_1_7,
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.compat_props = (GlobalProperty[]) {
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PC_COMPAT_1_7,
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{ /* end of list */ }
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},
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};
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#define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
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static QEMUMachine pc_q35_machine_v1_6 = {
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PC_Q35_1_6_MACHINE_OPTIONS,
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.name = "pc-q35-1.6",
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.init = pc_q35_init_1_6,
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.compat_props = (GlobalProperty[]) {
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PC_COMPAT_1_6,
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{ /* end of list */ }
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},
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};
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static QEMUMachine pc_q35_machine_v1_5 = {
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PC_Q35_1_6_MACHINE_OPTIONS,
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.name = "pc-q35-1.5",
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.init = pc_q35_init_1_5,
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.compat_props = (GlobalProperty[]) {
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PC_COMPAT_1_5,
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{ /* end of list */ }
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},
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};
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#define PC_Q35_1_4_MACHINE_OPTIONS \
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PC_Q35_1_6_MACHINE_OPTIONS, \
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.hot_add_cpu = NULL
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static QEMUMachine pc_q35_machine_v1_4 = {
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PC_Q35_1_4_MACHINE_OPTIONS,
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.name = "pc-q35-1.4",
|
|
.init = pc_q35_init_1_4,
|
|
.compat_props = (GlobalProperty[]) {
|
|
PC_COMPAT_1_4,
|
|
{ /* end of list */ }
|
|
},
|
|
};
|
|
|
|
static void pc_q35_machine_init(void)
|
|
{
|
|
qemu_register_pc_machine(&pc_q35_machine_v2_2);
|
|
qemu_register_pc_machine(&pc_q35_machine_v2_1);
|
|
qemu_register_pc_machine(&pc_q35_machine_v2_0);
|
|
qemu_register_pc_machine(&pc_q35_machine_v1_7);
|
|
qemu_register_pc_machine(&pc_q35_machine_v1_6);
|
|
qemu_register_pc_machine(&pc_q35_machine_v1_5);
|
|
qemu_register_pc_machine(&pc_q35_machine_v1_4);
|
|
}
|
|
|
|
machine_init(pc_q35_machine_init);
|