Jamin Lin bdb3748dba aspeed/smc: Add AST2700 support ... AST2700 fmc/spi controller's address decoding unit is 64KB and only bits [31:16] are used for decoding. Introduce seg_to_reg and reg_to_seg handlers for ast2700 fmc/spi controller. In addition, adds ast2700 fmc, spi0, spi1, and spi2 class init handler. AST2700 is a 64 bits quad core CPUs(Cortex-a35). Introduce a new "aspeed_2700_smc_flash_ops" and set its valid "max_access_size" 8 for 64 bits data format access. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>		2024-06-16 21:08:54 +02:00
..
aspeed_smc.c	aspeed/smc: Add AST2700 support	2024-06-16 21:08:54 +02:00
bcm2835_spi.c
ibex_spi_host.c
imx_spi.c	hw/misc/imx: Replace sprintf() by snprintf()	2024-04-25 12:48:12 +02:00
Kconfig
meson.build
mss-spi.c
npcm7xx_fiu.c	hw, target: Add ResetType argument to hold and exit phase methods	2024-04-25 10:21:06 +01:00
npcm_pspi.c
omap_spi.c
pl022.c
sifive_spi.c
ssi.c
stm32f2xx_spi.c
trace-events	aspeed/smc: support 64 bits dma dram address	2024-06-16 21:08:54 +02:00
trace.h
xilinx_spi.c
xilinx_spips.c
xlnx-versal-ospi.c