371 lines
11 KiB
C
371 lines
11 KiB
C
/*
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* MicroBlaze virtual CPU header
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*
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* Copyright (c) 2009 Edgar E. Iglesias
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_MICROBLAZE_H
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#define CPU_MICROBLAZE_H
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#define TARGET_LONG_BITS 32
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#define CPUState struct CPUMBState
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#include "cpu-defs.h"
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#include "softfloat.h"
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struct CPUMBState;
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#if !defined(CONFIG_USER_ONLY)
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#include "mmu.h"
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#endif
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#define TARGET_HAS_ICE 1
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#define ELF_MACHINE EM_MICROBLAZE
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#define EXCP_NMI 1
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#define EXCP_MMU 2
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#define EXCP_IRQ 3
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#define EXCP_BREAK 4
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#define EXCP_HW_BREAK 5
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#define EXCP_HW_EXCP 6
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/* MicroBlaze-specific interrupt pending bits. */
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#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
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/* Register aliases. R0 - R15 */
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#define R_SP 1
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#define SR_PC 0
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#define SR_MSR 1
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#define SR_EAR 3
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#define SR_ESR 5
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#define SR_FSR 7
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#define SR_BTR 0xb
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#define SR_EDR 0xd
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/* MSR flags. */
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#define MSR_BE (1<<0) /* 0x001 */
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#define MSR_IE (1<<1) /* 0x002 */
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#define MSR_C (1<<2) /* 0x004 */
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#define MSR_BIP (1<<3) /* 0x008 */
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#define MSR_FSL (1<<4) /* 0x010 */
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#define MSR_ICE (1<<5) /* 0x020 */
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#define MSR_DZ (1<<6) /* 0x040 */
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#define MSR_DCE (1<<7) /* 0x080 */
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#define MSR_EE (1<<8) /* 0x100 */
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#define MSR_EIP (1<<9) /* 0x200 */
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#define MSR_PVR (1<<10) /* 0x400 */
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#define MSR_CC (1<<31)
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/* Machine State Register (MSR) Fields */
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#define MSR_UM (1<<11) /* User Mode */
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#define MSR_UMS (1<<12) /* User Mode Save */
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#define MSR_VM (1<<13) /* Virtual Mode */
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#define MSR_VMS (1<<14) /* Virtual Mode Save */
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#define MSR_KERNEL MSR_EE|MSR_VM
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//#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE
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#define MSR_KERNEL_VMS MSR_EE|MSR_VMS
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//#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
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/* Exception State Register (ESR) Fields */
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#define ESR_DIZ (1<<11) /* Zone Protection */
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#define ESR_S (1<<10) /* Store instruction */
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#define ESR_ESS_FSL_OFFSET 5
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#define ESR_EC_FSL 0
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#define ESR_EC_UNALIGNED_DATA 1
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#define ESR_EC_ILLEGAL_OP 2
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#define ESR_EC_INSN_BUS 3
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#define ESR_EC_DATA_BUS 4
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#define ESR_EC_DIVZERO 5
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#define ESR_EC_FPU 6
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#define ESR_EC_PRIVINSN 7
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#define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
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#define ESR_EC_DATA_STORAGE 8
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#define ESR_EC_INSN_STORAGE 9
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#define ESR_EC_DATA_TLB 10
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#define ESR_EC_INSN_TLB 11
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#define ESR_EC_MASK 31
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/* Floating Point Status Register (FSR) Bits */
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#define FSR_IO (1<<4) /* Invalid operation */
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#define FSR_DZ (1<<3) /* Divide-by-zero */
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#define FSR_OF (1<<2) /* Overflow */
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#define FSR_UF (1<<1) /* Underflow */
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#define FSR_DO (1<<0) /* Denormalized operand error */
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/* Version reg. */
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/* Basic PVR mask */
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#define PVR0_PVR_FULL_MASK 0x80000000
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#define PVR0_USE_BARREL_MASK 0x40000000
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#define PVR0_USE_DIV_MASK 0x20000000
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#define PVR0_USE_HW_MUL_MASK 0x10000000
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#define PVR0_USE_FPU_MASK 0x08000000
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#define PVR0_USE_EXC_MASK 0x04000000
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#define PVR0_USE_ICACHE_MASK 0x02000000
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#define PVR0_USE_DCACHE_MASK 0x01000000
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#define PVR0_USE_MMU 0x00800000 /* new */
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#define PVR0_USE_BTC 0x00400000
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#define PVR0_ENDI 0x00200000
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#define PVR0_FAULT 0x00100000
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#define PVR0_VERSION_MASK 0x0000FF00
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#define PVR0_USER1_MASK 0x000000FF
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/* User 2 PVR mask */
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#define PVR1_USER2_MASK 0xFFFFFFFF
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/* Configuration PVR masks */
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#define PVR2_D_OPB_MASK 0x80000000
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#define PVR2_D_LMB_MASK 0x40000000
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#define PVR2_I_OPB_MASK 0x20000000
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#define PVR2_I_LMB_MASK 0x10000000
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#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
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#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
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#define PVR2_D_PLB_MASK 0x02000000 /* new */
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#define PVR2_I_PLB_MASK 0x01000000 /* new */
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#define PVR2_INTERCONNECT 0x00800000 /* new */
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#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
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#define PVR2_USE_FSL_EXC 0x00040000 /* new */
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#define PVR2_USE_MSR_INSTR 0x00020000
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#define PVR2_USE_PCMP_INSTR 0x00010000
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#define PVR2_AREA_OPTIMISED 0x00008000
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#define PVR2_USE_BARREL_MASK 0x00004000
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#define PVR2_USE_DIV_MASK 0x00002000
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#define PVR2_USE_HW_MUL_MASK 0x00001000
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#define PVR2_USE_FPU_MASK 0x00000800
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#define PVR2_USE_MUL64_MASK 0x00000400
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#define PVR2_USE_FPU2_MASK 0x00000200 /* new */
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#define PVR2_USE_IPLBEXC 0x00000100
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#define PVR2_USE_DPLBEXC 0x00000080
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#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
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#define PVR2_UNALIGNED_EXC_MASK 0x00000020
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#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
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#define PVR2_IOPB_BUS_EXC_MASK 0x00000008
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#define PVR2_DOPB_BUS_EXC_MASK 0x00000004
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#define PVR2_DIV_ZERO_EXC_MASK 0x00000002
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#define PVR2_FPU_EXC_MASK 0x00000001
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/* Debug and exception PVR masks */
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#define PVR3_DEBUG_ENABLED_MASK 0x80000000
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#define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
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#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
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#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
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#define PVR3_FSL_LINKS_MASK 0x00000380
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/* ICache config PVR masks */
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#define PVR4_USE_ICACHE_MASK 0x80000000
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#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
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#define PVR4_ICACHE_USE_FSL_MASK 0x02000000
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#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
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#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
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#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
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/* DCache config PVR masks */
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#define PVR5_USE_DCACHE_MASK 0x80000000
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#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
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#define PVR5_DCACHE_USE_FSL_MASK 0x02000000
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#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
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#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
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#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
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#define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
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/* ICache base address PVR mask */
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#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
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/* ICache high address PVR mask */
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#define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
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/* DCache base address PVR mask */
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#define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
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/* DCache high address PVR mask */
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#define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
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/* Target family PVR mask */
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#define PVR10_TARGET_FAMILY_MASK 0xFF000000
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/* MMU descrtiption */
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#define PVR11_USE_MMU 0xC0000000
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#define PVR11_MMU_ITLB_SIZE 0x38000000
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#define PVR11_MMU_DTLB_SIZE 0x07000000
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#define PVR11_MMU_TLB_ACCESS 0x00C00000
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#define PVR11_MMU_ZONES 0x003E0000
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/* MSR Reset value PVR mask */
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#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
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/* CPU flags. */
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/* Condition codes. */
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#define CC_GE 5
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#define CC_GT 4
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#define CC_LE 3
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#define CC_LT 2
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#define CC_NE 1
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#define CC_EQ 0
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#define NB_MMU_MODES 3
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#define STREAM_EXCEPTION (1 << 0)
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#define STREAM_ATOMIC (1 << 1)
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#define STREAM_TEST (1 << 2)
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#define STREAM_CONTROL (1 << 3)
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#define STREAM_NONBLOCK (1 << 4)
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typedef struct CPUMBState {
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uint32_t debug;
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uint32_t btaken;
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uint32_t btarget;
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uint32_t bimm;
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uint32_t imm;
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uint32_t regs[33];
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uint32_t sregs[24];
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float_status fp_status;
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/* Stack protectors. Yes, it's a hw feature. */
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uint32_t slr, shr;
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/* Internal flags. */
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#define IMM_FLAG 4
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#define MSR_EE_FLAG (1 << 8)
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#define DRTI_FLAG (1 << 16)
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#define DRTE_FLAG (1 << 17)
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#define DRTB_FLAG (1 << 18)
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#define D_FLAG (1 << 19) /* Bit in ESR. */
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/* TB dependent CPUState. */
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#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
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uint32_t iflags;
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struct {
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uint32_t regs[16];
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} pvr;
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#if !defined(CONFIG_USER_ONLY)
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/* Unified MMU. */
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struct microblaze_mmu mmu;
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#endif
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CPU_COMMON
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} CPUMBState;
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CPUState *cpu_mb_init(const char *cpu_model);
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int cpu_mb_exec(CPUState *s);
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void cpu_mb_close(CPUState *s);
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void do_interrupt(CPUState *env);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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int cpu_mb_signal_handler(int host_signum, void *pinfo,
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void *puc);
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enum {
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CC_OP_DYNAMIC, /* Use env->cc_op */
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CC_OP_FLAGS,
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CC_OP_CMP,
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};
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/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
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#define TARGET_PAGE_BITS 12
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#define MMAP_SHIFT TARGET_PAGE_BITS
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#define cpu_init cpu_mb_init
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#define cpu_exec cpu_mb_exec
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#define cpu_gen_code cpu_mb_gen_code
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#define cpu_signal_handler cpu_mb_signal_handler
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#define CPU_SAVE_VERSION 1
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _nommu
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#define MMU_MODE1_SUFFIX _kernel
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#define MMU_MODE2_SUFFIX _user
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#define MMU_NOMMU_IDX 0
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#define MMU_KERNEL_IDX 1
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#define MMU_USER_IDX 2
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/* See NB_MMU_MODES further up the file. */
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static inline int cpu_mmu_index (CPUState *env)
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{
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/* Are we in nommu mode?. */
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if (!(env->sregs[SR_MSR] & MSR_VM))
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return MMU_NOMMU_IDX;
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if (env->sregs[SR_MSR] & MSR_UM)
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return MMU_USER_IDX;
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return MMU_KERNEL_IDX;
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}
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int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
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int mmu_idx);
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#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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{
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if (newsp)
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env->regs[R_SP] = newsp;
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env->regs[3] = 0;
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}
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#endif
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static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
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{
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}
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static inline int cpu_interrupts_enabled(CPUState *env)
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{
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return env->sregs[SR_MSR] & MSR_IE;
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}
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#include "cpu-all.h"
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static inline target_ulong cpu_get_pc(CPUState *env)
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{
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return env->sregs[SR_PC];
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}
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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*pc = env->sregs[SR_PC];
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*cs_base = 0;
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*flags = (env->iflags & IFLAGS_TB_MASK) |
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(env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
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}
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#if !defined(CONFIG_USER_ONLY)
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void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
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int is_write, int is_exec, int is_asi, int size);
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#endif
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static inline bool cpu_has_work(CPUState *env)
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{
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return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
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}
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#include "exec-all.h"
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static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
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{
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env->sregs[SR_PC] = tb->pc;
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}
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#endif
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