f7697f0e62
Add basic CPU state description to the newly created machine.c Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-3-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
62 lines
1.6 KiB
C
62 lines
1.6 KiB
C
/*
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* QEMU RISC-V CPU -- internal functions and types
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*
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* Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_CPU_INTERNALS_H
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#define RISCV_CPU_INTERNALS_H
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#include "hw/registerfields.h"
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/* share data between vector helpers and decode code */
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FIELD(VDATA, MLEN, 0, 8)
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FIELD(VDATA, VM, 8, 1)
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FIELD(VDATA, LMUL, 9, 2)
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FIELD(VDATA, NF, 11, 4)
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FIELD(VDATA, WD, 11, 1)
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/* float point classify helpers */
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target_ulong fclass_h(uint64_t frs1);
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target_ulong fclass_s(uint64_t frs1);
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target_ulong fclass_d(uint64_t frs1);
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#define SEW8 0
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#define SEW16 1
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#define SEW32 2
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#define SEW64 3
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#ifndef CONFIG_USER_ONLY
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extern const VMStateDescription vmstate_riscv_cpu;
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#endif
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static inline uint64_t nanbox_s(float32 f)
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{
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return f | MAKE_64BIT_MASK(32, 32);
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}
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static inline float32 check_nanbox_s(uint64_t f)
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{
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uint64_t mask = MAKE_64BIT_MASK(32, 32);
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if (likely((f & mask) == mask)) {
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return (uint32_t)f;
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} else {
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return 0x7fc00000u; /* default qnan */
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}
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}
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#endif
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