qemu/tests/tcg/ppc64le/non_signalling_xscv.c
Matheus Ferst 68455cf593 tests/tcg/ppc64le: Use Altivec register names in clobber list
LLVM/Clang doesn't know the VSX registers when compiling with
-mabi=elfv1. Use only registers >= 32 and list them with their Altivec
name.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220304165417.1981159-6-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05 07:16:46 +01:00

38 lines
1.7 KiB
C

#include <stdio.h>
#include <stdint.h>
#include <inttypes.h>
#include <assert.h>
#define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \
do { \
uint64_t th, tl, bh = B_HI, bl = B_LO; \
asm("mtvsrd 32, %2\n\t" \
"mtvsrd 33, %3\n\t" \
"xxmrghd 32, 32, 33\n\t" \
INSN " 32, 32\n\t" \
"mfvsrd %0, 32\n\t" \
"xxswapd 32, 32\n\t" \
"mfvsrd %1, 32\n\t" \
: "=r" (th), "=r" (tl) \
: "r" (bh), "r" (bl) \
: "v0", "v1"); \
printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") = 0x%016" PRIx64 \
"%016" PRIx64 "\n", bh, bl, th, tl); \
assert(th == T_HI && tl == T_LO); \
} while (0)
int main(void)
{
/* SNaN shouldn't be silenced */
TEST("xscvspdpn", 0x7fbfffff00000000ULL, 0x0, 0x7ff7ffffe0000000ULL, 0x0);
TEST("xscvdpspn", 0x7ff7ffffffffffffULL, 0x0, 0x7fbfffff7fbfffffULL, 0x0);
/*
* SNaN inputs having no significant bits in the upper 23 bits of the
* signifcand will return Infinity as the result.
*/
TEST("xscvdpspn", 0x7ff000001fffffffULL, 0x0, 0x7f8000007f800000ULL, 0x0);
return 0;
}