Richard Henderson e7face702a accel/tcg: Add insn_start to DisasContextBase ...

This is currently target-specific for many; begin making it
target independent.

Tested-by: Jørgen Hansen <Jorgen.Hansen@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

2024-04-09 07:45:05 -10:00

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user

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address-spaces.h

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confidential-guest-support.h

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cpu_ldst.h

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cpu-all.h

accel/tcg: Add TLB_CHECK_ALIGNED

2024-03-05 13:22:56 +00:00

cpu-common.h

cpu: Remove page_size_init

2024-02-29 11:35:37 -10:00

cpu-defs.h

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cputlb.h

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exec-all.h

physmem: Expose tlb_reset_dirty_range_all()

2024-03-12 17:39:40 -04:00

gdbstub.h

gdbstub: expose api to find registers

2024-02-28 09:11:42 +00:00

helper-gen-common.h

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helper-gen.h

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helper-gen.h.inc

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helper-head.h

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helper-info.c.inc

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helper-proto-common.h

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helper-proto.h

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helper-proto.h.inc

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hwaddr.h

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ioport.h

exec/ioport: Add portio_list_set_enabled()

2024-02-14 06:09:32 -05:00

log.h

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memattrs.h

accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull

2024-03-05 13:22:56 +00:00

memop.h

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memopidx.h

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memory_ldst_cached.h.inc

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memory_ldst_phys.h.inc

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memory_ldst.h.inc

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memory-internal.h

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memory.h

include/exec/memory.h: correct typos

2024-02-21 08:16:43 +03:00

page-vary.h

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plugin-gen.h

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poison.h

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ram_addr.h

physmem: Fix migration dirty bitmap coherency with TCG memory access

2024-03-12 17:39:40 -04:00

ramblock.h

migration/ram: Add outgoing 'mapped-ram' migration

2024-03-01 15:42:04 +08:00

ramlist.h

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replay-core.h

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target_long.h

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target_page.h

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tb-flush.h

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tlb-common.h

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translate-all.h

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translation-block.h

tcg: Make tb_cflags() usable from target-agnostic code

2024-01-29 21:04:10 +10:00

translator.h

accel/tcg: Add insn_start to DisasContextBase

2024-04-09 07:45:05 -10:00

tswap.h

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vaddr.h

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