qemu/target
Peter Maydell e784807cd2 target/arm: Do hflags rebuild in cpsr_write()
Currently we rely on all the callsites of cpsr_write() to rebuild the
cached hflags if they change one of the CPSR bits which we use as a
TB flag and cache in hflags.  This is a bit awkward when we want to
change the set of CPSR bits that we cache, because it means we need
to re-audit all the cpsr_write() callsites to see which flags they
are writing and whether they now need to rebuild the hflags.

Switch instead to making cpsr_write() call arm_rebuild_hflags()
itself if one of the bits being changed is a cached bit.

We don't do the rebuild for the CPSRWriteRaw write type, because that
kind of write is generally doing something special anyway.  For the
CPSRWriteRaw callsites in the KVM code and inbound migration we
definitely don't want to recalculate the hflags; the callsites in
boot.c and arm-powerctl.c have to do a rebuild-hflags call themselves
anyway because of other CPU state changes they make.

This allows us to drop explicit arm_rebuild_hflags() calls in a
couple of places where the only reason we needed to call it was the
CPSR write.

This fixes a bug where we were incorrectly failing to rebuild hflags
in the code path for a gdbstub write to CPSR, which meant that you
could make QEMU assert by breaking into a running guest, altering the
CPSR to change the value of, for example, CPSR.E, and then
continuing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210817201843.3829-1-peter.maydell@linaro.org
2021-08-26 17:02:01 +01:00
..
alpha accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
arm target/arm: Do hflags rebuild in cpsr_write() 2021-08-26 17:02:01 +01:00
avr accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
cris accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
hexagon The Hexagon target was silently failing the SIGSEGV test because 2021-07-26 13:36:51 +01:00
hppa accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
i386 i386/cpu: Remove AVX_VNNI feature from Cooperlake cpu model 2021-08-25 12:36:49 -04:00
m68k accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
microblaze accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
mips target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian() 2021-08-25 13:02:14 +02:00
nios2 target/nios2: Mark raise_exception() as noreturn 2021-07-30 08:23:12 -10:00
openrisc accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
ppc arch_init.h: Don't include arch_init.h unnecessarily 2021-08-26 17:02:00 +01:00
riscv accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
rx accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
s390x arch_init.h: Don't include arch_init.h unnecessarily 2021-08-26 17:02:00 +01:00
sh4 accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
sparc accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
tricore accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
xtensa accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00