Philippe Mathieu-Daudé 18f86aecd6 target/mips: Fix TX79 LQ/SQ opcodes ...

The base register address offset is *signed*.

Cc: qemu-stable@nongnu.org
Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914090447.12557-1-philmd@linaro.org>

2023-11-07 12:13:28 +01:00

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sysemu

hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h'

2023-10-19 23:13:27 +02:00

dsp_helper.c

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exception.c

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fpu_helper.c

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lcsr_translate.c

tcg: Rename cpu_env to tcg_env

2023-10-03 08:01:02 -07:00

lcsr.decode

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ldst_helper.c

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lmmi_helper.c

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meson.build

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micromips_translate.c.inc

tcg: Rename cpu_env to tcg_env

2023-10-03 08:01:02 -07:00

mips16e_translate.c.inc

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msa_helper.c

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msa_helper.h.inc

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msa_translate.c

tcg: Rename cpu_env to tcg_env

2023-10-03 08:01:02 -07:00

msa.decode

target/mips: Fix MSA BZ/BNZ opcodes displacement

2023-11-07 12:13:28 +01:00

mxu_translate.c

tcg: Rename cpu_env to tcg_env

2023-10-03 08:01:02 -07:00

nanomips_translate.c.inc

tcg: Rename cpu_env to tcg_env

2023-10-03 08:01:02 -07:00

octeon_translate.c

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octeon.decode

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op_helper.c

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rel6_translate.c

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rel6.decode

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sysemu_helper.h.inc

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tcg-internal.h

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trace-events

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trace.h

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translate_addr_const.c

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translate.c

accel/tcg: Replace CPUState.env_ptr with cpu_env()

2023-10-04 11:03:54 -07:00

translate.h

tcg: Rename cpu_env to tcg_env

2023-10-03 08:01:02 -07:00

tx79_translate.c

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tx79.decode

target/mips: Fix TX79 LQ/SQ opcodes

2023-11-07 12:13:28 +01:00

txx9_translate.c

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vr54xx_helper.c

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vr54xx_helper.h.inc

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vr54xx_translate.c

tcg: Rename cpu_env to tcg_env

2023-10-03 08:01:02 -07:00

vr54xx.decode

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