8e4b4c1ca6
The AN524 version of the SCC interface has different behaviour for
some of the CFG registers; implement it.
Each board in this family can have minor differences in the meaning
of the CFG registers, so rather than trying to specify all the
possible semantics via individual device properties, we make the
behaviour conditional on the part-number field of the SCC_ID register
which the board code already passes us.
For the AN524, the differences are:
* CFG3 is reserved rather than being board switches
* CFG5 is a new register ("ACLK Frequency in Hz")
* CFG6 is a new register ("Clock divider for BRAM")
We implement both of the new registers as reads-as-written.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-11-peter.maydell@linaro.org
49 lines
962 B
C
49 lines
962 B
C
/*
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* ARM MPS2 SCC emulation
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*
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* Copyright (c) 2017 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#ifndef MPS2_SCC_H
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#define MPS2_SCC_H
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#include "hw/sysbus.h"
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#include "hw/misc/led.h"
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#include "qom/object.h"
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#define TYPE_MPS2_SCC "mps2-scc"
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OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC)
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struct MPS2SCC {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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LEDState *led[8];
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uint32_t cfg0;
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uint32_t cfg1;
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uint32_t cfg2;
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uint32_t cfg4;
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uint32_t cfg5;
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uint32_t cfg6;
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uint32_t cfgdata_rtn;
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uint32_t cfgdata_out;
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uint32_t cfgctrl;
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uint32_t cfgstat;
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uint32_t dll;
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uint32_t aid;
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uint32_t id;
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uint32_t num_oscclk;
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uint32_t *oscclk;
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uint32_t *oscclk_reset;
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};
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#endif
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