Michael Clark e6b8552c65
SiFive RISC-V PRCI Block
Simple model of the PRCI  (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07 08:30:28 +13:00
..
2018-03-02 13:45:50 -06:00
2018-03-02 13:45:50 -06:00
2018-03-05 14:27:24 +00:00
2018-03-02 13:45:50 -06:00
2018-03-07 08:30:28 +13:00
2018-03-02 13:45:50 -06:00
2018-03-02 13:45:50 -06:00
2018-03-02 13:45:50 -06:00