fd6a543d19
This function reads the value of the PCI_CLASS_PROG register for PCI IDE controllers and configures the PCI BARs and/or IDE ioports accordingly. In the case where we switch to legacy mode, the PCI BARs are set to return zero (as suggested in the "PCI IDE Controller" specification), the legacy IDE ioports are enabled, and the PCI interrupt pin cleared to indicate legacy IRQ routing. Conversely when we switch to native mode, the legacy IDE ioports are disabled and the PCI interrupt pin set to indicate native IRQ routing. The contents of the PCI BARs are unspecified, but this is not an issue since if a PCI IDE controller has been switched to native mode then its BARs will need to be programmed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20231116103355.588580-3-mark.cave-ayland@ilande.co.uk> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
70 lines
1.7 KiB
C
70 lines
1.7 KiB
C
#ifndef HW_IDE_PCI_H
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#define HW_IDE_PCI_H
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#include "hw/ide/internal.h"
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#include "hw/pci/pci_device.h"
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#include "qom/object.h"
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#define BM_STATUS_DMAING 0x01
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#define BM_STATUS_ERROR 0x02
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#define BM_STATUS_INT 0x04
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#define BM_CMD_START 0x01
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#define BM_CMD_READ 0x08
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typedef struct BMDMAState {
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IDEDMA dma;
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uint8_t cmd;
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uint8_t status;
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uint32_t addr;
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IDEBus *bus;
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/* current transfer state */
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uint32_t cur_addr;
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uint32_t cur_prd_last;
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uint32_t cur_prd_addr;
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uint32_t cur_prd_len;
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BlockCompletionFunc *dma_cb;
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MemoryRegion addr_ioport;
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MemoryRegion extra_io;
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qemu_irq irq;
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/* Bit 0-2 and 7: BM status register
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* Bit 3-6: bus->error_status */
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uint8_t migration_compat_status;
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uint8_t migration_retry_unit;
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int64_t migration_retry_sector_num;
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uint32_t migration_retry_nsector;
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struct PCIIDEState *pci_dev;
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} BMDMAState;
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#define TYPE_PCI_IDE "pci-ide"
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OBJECT_DECLARE_SIMPLE_TYPE(PCIIDEState, PCI_IDE)
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struct PCIIDEState {
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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IDEBus bus[2];
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BMDMAState bmdma[2];
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qemu_irq isa_irq[2];
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uint32_t secondary; /* used only for cmd646 */
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MemoryRegion bmdma_bar;
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MemoryRegion cmd_bar[2];
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MemoryRegion data_bar[2];
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};
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void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d);
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void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val);
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void bmdma_status_writeb(BMDMAState *bm, uint32_t val);
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extern MemoryRegionOps bmdma_addr_ioport_ops;
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void pci_ide_create_devs(PCIDevice *dev);
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void pci_ide_update_mode(PCIIDEState *s);
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extern const VMStateDescription vmstate_ide_pci;
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extern const MemoryRegionOps pci_ide_cmd_le_ops;
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extern const MemoryRegionOps pci_ide_data_le_ops;
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#endif
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