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Richard Henderson b3eb5b861a target/riscv: Use QEMU_IOTHREAD_LOCK_GUARD in riscv_cpu_update_mip 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-04 16:20:01 -08:00
..
insn_trans
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
2022-09-27 11:23:57 +10:00
arch_dump.c
dump: Replace opaque DumpState pointer with a typed one
2022-10-06 19:30:43 +04:00
bitmanip_helper.c
…
common-semi-target.h
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cpu_bits.h
target/riscv: debug: Introduce tinfo CSR
2022-09-27 11:23:57 +10:00
cpu_helper.c
target/riscv: Use QEMU_IOTHREAD_LOCK_GUARD in riscv_cpu_update_mip
2023-01-04 16:20:01 -08:00
cpu_user.h
…
cpu-param.h
…
cpu.c
target/riscv: Convert to 3-phase reset
2022-12-16 15:58:15 +00:00
cpu.h
target/riscv: Convert to 3-phase reset
2022-12-16 15:58:15 +00:00
crypto_helper.c
…
csr.c
target/riscv: debug: Introduce tinfo CSR
2022-09-27 11:23:57 +10:00
debug.c
cleanup: Tweak and re-run return_directly.cocci
2022-12-14 16:19:35 +01:00
debug.h
target/riscv: debug: Add initial support of type 6 trigger
2022-09-27 11:23:57 +10:00
fpu_helper.c
…
gdbstub.c
target/riscv: Check the correct exception cause in vector GDB stub
2022-09-27 07:04:38 +10:00
helper.h
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
2022-09-27 11:23:57 +10:00
insn16.decode
target/riscv: fix shifts shamt value for rv128c
2022-09-07 09:18:32 +02:00
insn32.decode
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
2022-09-27 11:23:57 +10:00
instmap.h
target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
2022-09-07 09:18:32 +02:00
internals.h
target/riscv: rvv: Add mask agnostic for vv instructions
2022-09-07 09:18:32 +02:00
Kconfig
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kvm_riscv.h
…
kvm-stub.c
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kvm.c
kvm: allow target-specific accelerator properties
2022-10-10 09:23:16 +02:00
m128_helper.c
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machine.c
target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
2022-09-27 11:23:57 +10:00
meson.build
target/riscv: Add stimecmp support
2022-09-07 09:19:15 +02:00
monitor.c
…
op_helper.c
…
pmp.c
target/riscv: pmp: Fixup TLB size calculation
2022-10-14 14:36:19 +10:00
pmp.h
…
pmu.c
hw/riscv: virt: Add PMU DT node to the device tree
2022-09-07 09:19:15 +02:00
pmu.h
hw/riscv: virt: Add PMU DT node to the device tree
2022-09-07 09:19:15 +02:00
sbi_ecall_interface.h
…
time_helper.c
target/riscv: Add vstimecmp support
2022-09-07 09:19:15 +02:00
time_helper.h
target/riscv: Add stimecmp support
2022-09-07 09:19:15 +02:00
trace-events
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trace.h
…
translate.c
target/riscv: Honour -semihosting-config userspace=on and enable=on
2022-09-13 17:18:21 +01:00
vector_helper.c
cleanup: Tweak and re-run return_directly.cocci
2022-12-14 16:19:35 +01:00
XVentanaCondOps.decode
…