e61dc8f72c
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK and BREAK.N instructions and IBREAK breakpoints. IBREAK breakpoint address is considered constant for TB lifetime. On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
703 lines
19 KiB
C
703 lines
19 KiB
C
/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu.h"
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#include "dyngen-exec.h"
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#include "helpers.h"
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#include "host-utils.h"
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static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
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void *retaddr);
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#define ALIGNED_ONLY
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#define MMUSUFFIX _mmu
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#define SHIFT 0
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#include "softmmu_template.h"
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#define SHIFT 1
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#include "softmmu_template.h"
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#define SHIFT 2
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#include "softmmu_template.h"
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#define SHIFT 3
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#include "softmmu_template.h"
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static void do_restore_state(void *pc_ptr)
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{
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TranslationBlock *tb;
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uint32_t pc = (uint32_t)(intptr_t)pc_ptr;
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tb = tb_find_pc(pc);
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if (tb) {
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cpu_restore_state(tb, env, pc);
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}
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}
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static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
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void *retaddr)
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{
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
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!xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
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do_restore_state(retaddr);
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HELPER(exception_cause_vaddr)(
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env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
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}
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}
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void tlb_fill(CPUState *env1, target_ulong vaddr, int is_write, int mmu_idx,
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void *retaddr)
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{
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CPUState *saved_env = env;
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env = env1;
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{
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uint32_t paddr;
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uint32_t page_size;
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unsigned access;
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int ret = xtensa_get_physical_addr(env, vaddr, is_write, mmu_idx,
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&paddr, &page_size, &access);
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qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__,
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vaddr, is_write, mmu_idx, paddr, ret);
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if (ret == 0) {
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tlb_set_page(env,
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vaddr & TARGET_PAGE_MASK,
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paddr & TARGET_PAGE_MASK,
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access, mmu_idx, page_size);
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} else {
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do_restore_state(retaddr);
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HELPER(exception_cause_vaddr)(env->pc, ret, vaddr);
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}
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}
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env = saved_env;
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}
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void HELPER(exception)(uint32_t excp)
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{
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env->exception_index = excp;
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cpu_loop_exit(env);
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}
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void HELPER(exception_cause)(uint32_t pc, uint32_t cause)
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{
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uint32_t vector;
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env->pc = pc;
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if (env->sregs[PS] & PS_EXCM) {
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if (env->config->ndepc) {
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env->sregs[DEPC] = pc;
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} else {
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env->sregs[EPC1] = pc;
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}
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vector = EXC_DOUBLE;
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} else {
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env->sregs[EPC1] = pc;
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vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
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}
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env->sregs[EXCCAUSE] = cause;
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env->sregs[PS] |= PS_EXCM;
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HELPER(exception)(vector);
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}
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void HELPER(exception_cause_vaddr)(uint32_t pc, uint32_t cause, uint32_t vaddr)
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{
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env->sregs[EXCVADDR] = vaddr;
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HELPER(exception_cause)(pc, cause);
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}
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void HELPER(debug_exception)(uint32_t pc, uint32_t cause)
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{
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unsigned level = env->config->debug_level;
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env->pc = pc;
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env->sregs[DEBUGCAUSE] = cause;
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env->sregs[EPC1 + level - 1] = pc;
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env->sregs[EPS2 + level - 2] = env->sregs[PS];
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env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
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(level << PS_INTLEVEL_SHIFT);
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HELPER(exception)(EXC_DEBUG);
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}
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uint32_t HELPER(nsa)(uint32_t v)
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{
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if (v & 0x80000000) {
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v = ~v;
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}
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return v ? clz32(v) - 1 : 31;
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}
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uint32_t HELPER(nsau)(uint32_t v)
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{
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return v ? clz32(v) : 32;
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}
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static void copy_window_from_phys(CPUState *env,
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uint32_t window, uint32_t phys, uint32_t n)
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{
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assert(phys < env->config->nareg);
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if (phys + n <= env->config->nareg) {
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memcpy(env->regs + window, env->phys_regs + phys,
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n * sizeof(uint32_t));
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} else {
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uint32_t n1 = env->config->nareg - phys;
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memcpy(env->regs + window, env->phys_regs + phys,
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n1 * sizeof(uint32_t));
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memcpy(env->regs + window + n1, env->phys_regs,
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(n - n1) * sizeof(uint32_t));
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}
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}
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static void copy_phys_from_window(CPUState *env,
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uint32_t phys, uint32_t window, uint32_t n)
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{
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assert(phys < env->config->nareg);
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if (phys + n <= env->config->nareg) {
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memcpy(env->phys_regs + phys, env->regs + window,
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n * sizeof(uint32_t));
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} else {
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uint32_t n1 = env->config->nareg - phys;
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memcpy(env->phys_regs + phys, env->regs + window,
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n1 * sizeof(uint32_t));
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memcpy(env->phys_regs, env->regs + window + n1,
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(n - n1) * sizeof(uint32_t));
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}
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}
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static inline unsigned windowbase_bound(unsigned a, const CPUState *env)
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{
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return a & (env->config->nareg / 4 - 1);
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}
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static inline unsigned windowstart_bit(unsigned a, const CPUState *env)
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{
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return 1 << windowbase_bound(a, env);
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}
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void xtensa_sync_window_from_phys(CPUState *env)
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{
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copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
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}
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void xtensa_sync_phys_from_window(CPUState *env)
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{
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copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
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}
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static void rotate_window_abs(uint32_t position)
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{
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xtensa_sync_phys_from_window(env);
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env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
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xtensa_sync_window_from_phys(env);
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}
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static void rotate_window(uint32_t delta)
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{
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rotate_window_abs(env->sregs[WINDOW_BASE] + delta);
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}
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void HELPER(wsr_windowbase)(uint32_t v)
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{
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rotate_window_abs(v);
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}
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void HELPER(entry)(uint32_t pc, uint32_t s, uint32_t imm)
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{
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int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
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if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
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qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
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pc, env->sregs[PS]);
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HELPER(exception_cause)(pc, ILLEGAL_INSTRUCTION_CAUSE);
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} else {
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env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
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rotate_window(callinc);
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env->sregs[WINDOW_START] |=
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windowstart_bit(env->sregs[WINDOW_BASE], env);
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}
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}
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void HELPER(window_check)(uint32_t pc, uint32_t w)
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{
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uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
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uint32_t windowstart = env->sregs[WINDOW_START];
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uint32_t m, n;
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if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) {
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return;
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}
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for (n = 1; ; ++n) {
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if (n > w) {
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return;
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}
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if (windowstart & windowstart_bit(windowbase + n, env)) {
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break;
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}
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}
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m = windowbase_bound(windowbase + n, env);
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rotate_window(n);
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env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
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(windowbase << PS_OWB_SHIFT) | PS_EXCM;
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env->sregs[EPC1] = env->pc = pc;
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if (windowstart & windowstart_bit(m + 1, env)) {
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HELPER(exception)(EXC_WINDOW_OVERFLOW4);
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} else if (windowstart & windowstart_bit(m + 2, env)) {
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HELPER(exception)(EXC_WINDOW_OVERFLOW8);
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} else {
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HELPER(exception)(EXC_WINDOW_OVERFLOW12);
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}
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}
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uint32_t HELPER(retw)(uint32_t pc)
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{
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int n = (env->regs[0] >> 30) & 0x3;
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int m = 0;
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uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
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uint32_t windowstart = env->sregs[WINDOW_START];
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uint32_t ret_pc = 0;
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if (windowstart & windowstart_bit(windowbase - 1, env)) {
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m = 1;
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} else if (windowstart & windowstart_bit(windowbase - 2, env)) {
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m = 2;
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} else if (windowstart & windowstart_bit(windowbase - 3, env)) {
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m = 3;
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}
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if (n == 0 || (m != 0 && m != n) ||
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((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
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qemu_log("Illegal retw instruction(pc = %08x), "
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"PS = %08x, m = %d, n = %d\n",
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pc, env->sregs[PS], m, n);
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HELPER(exception_cause)(pc, ILLEGAL_INSTRUCTION_CAUSE);
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} else {
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int owb = windowbase;
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ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
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rotate_window(-n);
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if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
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env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
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} else {
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/* window underflow */
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env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
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(windowbase << PS_OWB_SHIFT) | PS_EXCM;
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env->sregs[EPC1] = env->pc = pc;
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if (n == 1) {
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HELPER(exception)(EXC_WINDOW_UNDERFLOW4);
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} else if (n == 2) {
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HELPER(exception)(EXC_WINDOW_UNDERFLOW8);
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} else if (n == 3) {
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HELPER(exception)(EXC_WINDOW_UNDERFLOW12);
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}
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}
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}
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return ret_pc;
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}
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void HELPER(rotw)(uint32_t imm4)
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{
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rotate_window(imm4);
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}
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void HELPER(restore_owb)(void)
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{
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rotate_window_abs((env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
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}
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void HELPER(movsp)(uint32_t pc)
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{
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if ((env->sregs[WINDOW_START] &
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(windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
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windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
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windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
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HELPER(exception_cause)(pc, ALLOCA_CAUSE);
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}
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}
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void HELPER(wsr_lbeg)(uint32_t v)
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{
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if (env->sregs[LBEG] != v) {
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tb_invalidate_phys_page_range(
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env->sregs[LEND] - 1, env->sregs[LEND], 0);
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env->sregs[LBEG] = v;
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}
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}
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void HELPER(wsr_lend)(uint32_t v)
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{
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if (env->sregs[LEND] != v) {
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tb_invalidate_phys_page_range(
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env->sregs[LEND] - 1, env->sregs[LEND], 0);
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env->sregs[LEND] = v;
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tb_invalidate_phys_page_range(
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env->sregs[LEND] - 1, env->sregs[LEND], 0);
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}
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}
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void HELPER(dump_state)(void)
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{
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cpu_dump_state(env, stderr, fprintf, 0);
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}
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void HELPER(waiti)(uint32_t pc, uint32_t intlevel)
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{
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env->pc = pc;
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env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
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(intlevel << PS_INTLEVEL_SHIFT);
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check_interrupts(env);
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if (env->pending_irq_level) {
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cpu_loop_exit(env);
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return;
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}
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env->halt_clock = qemu_get_clock_ns(vm_clock);
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env->halted = 1;
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
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xtensa_rearm_ccompare_timer(env);
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}
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HELPER(exception)(EXCP_HLT);
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}
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void HELPER(timer_irq)(uint32_t id, uint32_t active)
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{
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xtensa_timer_irq(env, id, active);
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}
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void HELPER(advance_ccount)(uint32_t d)
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{
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xtensa_advance_ccount(env, d);
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}
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void HELPER(check_interrupts)(CPUState *env)
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{
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check_interrupts(env);
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}
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void HELPER(wsr_rasid)(uint32_t v)
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{
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v = (v & 0xffffff00) | 0x1;
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if (v != env->sregs[RASID]) {
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env->sregs[RASID] = v;
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tlb_flush(env, 1);
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}
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}
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static uint32_t get_page_size(const CPUState *env, bool dtlb, uint32_t way)
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{
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uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
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switch (way) {
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case 4:
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return (tlbcfg >> 16) & 0x3;
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case 5:
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return (tlbcfg >> 20) & 0x1;
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case 6:
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return (tlbcfg >> 24) & 0x1;
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default:
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return 0;
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}
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}
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/*!
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* Get bit mask for the virtual address bits translated by the TLB way
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*/
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uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way)
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{
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
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bool varway56 = dtlb ?
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env->config->dtlb.varway56 :
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env->config->itlb.varway56;
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switch (way) {
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case 4:
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return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
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case 5:
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if (varway56) {
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return 0xf8000000 << get_page_size(env, dtlb, way);
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} else {
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return 0xf8000000;
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}
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case 6:
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if (varway56) {
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return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
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} else {
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return 0xf0000000;
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}
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default:
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return 0xfffff000;
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}
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} else {
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return REGION_PAGE_MASK;
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}
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}
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/*!
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* Get bit mask for the 'VPN without index' field.
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* See ISA, 4.6.5.6, data format for RxTLB0
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*/
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static uint32_t get_vpn_mask(const CPUState *env, bool dtlb, uint32_t way)
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{
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if (way < 4) {
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bool is32 = (dtlb ?
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env->config->dtlb.nrefillentries :
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env->config->itlb.nrefillentries) == 32;
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return is32 ? 0xffff8000 : 0xffffc000;
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} else if (way == 4) {
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return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
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} else if (way <= 6) {
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uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
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bool varway56 = dtlb ?
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env->config->dtlb.varway56 :
|
|
env->config->itlb.varway56;
|
|
|
|
if (varway56) {
|
|
return mask << (way == 5 ? 2 : 3);
|
|
} else {
|
|
return mask << 1;
|
|
}
|
|
} else {
|
|
return 0xfffff000;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* Split virtual address into VPN (with index) and entry index
|
|
* for the given TLB way
|
|
*/
|
|
void split_tlb_entry_spec_way(const CPUState *env, uint32_t v, bool dtlb,
|
|
uint32_t *vpn, uint32_t wi, uint32_t *ei)
|
|
{
|
|
bool varway56 = dtlb ?
|
|
env->config->dtlb.varway56 :
|
|
env->config->itlb.varway56;
|
|
|
|
if (!dtlb) {
|
|
wi &= 7;
|
|
}
|
|
|
|
if (wi < 4) {
|
|
bool is32 = (dtlb ?
|
|
env->config->dtlb.nrefillentries :
|
|
env->config->itlb.nrefillentries) == 32;
|
|
*ei = (v >> 12) & (is32 ? 0x7 : 0x3);
|
|
} else {
|
|
switch (wi) {
|
|
case 4:
|
|
{
|
|
uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
|
|
*ei = (v >> eibase) & 0x3;
|
|
}
|
|
break;
|
|
|
|
case 5:
|
|
if (varway56) {
|
|
uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
|
|
*ei = (v >> eibase) & 0x3;
|
|
} else {
|
|
*ei = (v >> 27) & 0x1;
|
|
}
|
|
break;
|
|
|
|
case 6:
|
|
if (varway56) {
|
|
uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
|
|
*ei = (v >> eibase) & 0x7;
|
|
} else {
|
|
*ei = (v >> 28) & 0x1;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
*ei = 0;
|
|
break;
|
|
}
|
|
}
|
|
*vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
|
|
}
|
|
|
|
/*!
|
|
* Split TLB address into TLB way, entry index and VPN (with index).
|
|
* See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
|
|
*/
|
|
static void split_tlb_entry_spec(uint32_t v, bool dtlb,
|
|
uint32_t *vpn, uint32_t *wi, uint32_t *ei)
|
|
{
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
|
|
*wi = v & (dtlb ? 0xf : 0x7);
|
|
split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
|
|
} else {
|
|
*vpn = v & REGION_PAGE_MASK;
|
|
*wi = 0;
|
|
*ei = (v >> 29) & 0x7;
|
|
}
|
|
}
|
|
|
|
static xtensa_tlb_entry *get_tlb_entry(uint32_t v, bool dtlb, uint32_t *pwi)
|
|
{
|
|
uint32_t vpn;
|
|
uint32_t wi;
|
|
uint32_t ei;
|
|
|
|
split_tlb_entry_spec(v, dtlb, &vpn, &wi, &ei);
|
|
if (pwi) {
|
|
*pwi = wi;
|
|
}
|
|
return xtensa_tlb_get_entry(env, dtlb, wi, ei);
|
|
}
|
|
|
|
uint32_t HELPER(rtlb0)(uint32_t v, uint32_t dtlb)
|
|
{
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
|
|
uint32_t wi;
|
|
const xtensa_tlb_entry *entry = get_tlb_entry(v, dtlb, &wi);
|
|
return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
|
|
} else {
|
|
return v & REGION_PAGE_MASK;
|
|
}
|
|
}
|
|
|
|
uint32_t HELPER(rtlb1)(uint32_t v, uint32_t dtlb)
|
|
{
|
|
const xtensa_tlb_entry *entry = get_tlb_entry(v, dtlb, NULL);
|
|
return entry->paddr | entry->attr;
|
|
}
|
|
|
|
void HELPER(itlb)(uint32_t v, uint32_t dtlb)
|
|
{
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
|
|
uint32_t wi;
|
|
xtensa_tlb_entry *entry = get_tlb_entry(v, dtlb, &wi);
|
|
if (entry->variable && entry->asid) {
|
|
tlb_flush_page(env, entry->vaddr);
|
|
entry->asid = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb)
|
|
{
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
|
|
uint32_t wi;
|
|
uint32_t ei;
|
|
uint8_t ring;
|
|
int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
|
|
|
|
switch (res) {
|
|
case 0:
|
|
if (ring >= xtensa_get_ring(env)) {
|
|
return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
|
|
}
|
|
break;
|
|
|
|
case INST_TLB_MULTI_HIT_CAUSE:
|
|
case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
|
|
HELPER(exception_cause_vaddr)(env->pc, res, v);
|
|
break;
|
|
}
|
|
return 0;
|
|
} else {
|
|
return (v & REGION_PAGE_MASK) | 0x1;
|
|
}
|
|
}
|
|
|
|
void xtensa_tlb_set_entry(CPUState *env, bool dtlb,
|
|
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
|
|
{
|
|
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
|
|
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
|
|
if (entry->variable) {
|
|
if (entry->asid) {
|
|
tlb_flush_page(env, entry->vaddr);
|
|
}
|
|
entry->vaddr = vpn;
|
|
entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
|
|
entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
|
|
entry->attr = pte & 0xf;
|
|
} else {
|
|
qemu_log("%s %d, %d, %d trying to set immutable entry\n",
|
|
__func__, dtlb, wi, ei);
|
|
}
|
|
} else {
|
|
tlb_flush_page(env, entry->vaddr);
|
|
if (xtensa_option_enabled(env->config,
|
|
XTENSA_OPTION_REGION_TRANSLATION)) {
|
|
entry->paddr = pte & REGION_PAGE_MASK;
|
|
}
|
|
entry->attr = pte & 0xf;
|
|
}
|
|
}
|
|
|
|
void HELPER(wtlb)(uint32_t p, uint32_t v, uint32_t dtlb)
|
|
{
|
|
uint32_t vpn;
|
|
uint32_t wi;
|
|
uint32_t ei;
|
|
split_tlb_entry_spec(v, dtlb, &vpn, &wi, &ei);
|
|
xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
|
|
}
|
|
|
|
|
|
void HELPER(wsr_ibreakenable)(uint32_t v)
|
|
{
|
|
uint32_t change = v ^ env->sregs[IBREAKENABLE];
|
|
unsigned i;
|
|
|
|
for (i = 0; i < env->config->nibreak; ++i) {
|
|
if (change & (1 << i)) {
|
|
tb_invalidate_phys_page_range(
|
|
env->sregs[IBREAKA + i], env->sregs[IBREAKA + i] + 1, 0);
|
|
}
|
|
}
|
|
env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
|
|
}
|
|
|
|
void HELPER(wsr_ibreaka)(uint32_t i, uint32_t v)
|
|
{
|
|
if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
|
|
tb_invalidate_phys_page_range(
|
|
env->sregs[IBREAKA + i], env->sregs[IBREAKA + i] + 1, 0);
|
|
tb_invalidate_phys_page_range(v, v + 1, 0);
|
|
}
|
|
env->sregs[IBREAKA + i] = v;
|
|
}
|