e53fa62c17
XTFPGA boards should populate core memory regions the same way sim machine does. Move xtensa_create_memory_regions implementation to a separate file and use it to create instruction and data memory regions on XTFPGA boards. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
558 lines
18 KiB
C
558 lines
18 KiB
C
/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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#include "hw/char/serial.h"
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#include "net/net.h"
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#include "hw/sysbus.h"
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#include "hw/block/flash.h"
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#include "sysemu/block-backend.h"
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#include "chardev/char.h"
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#include "sysemu/device_tree.h"
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#include "qemu/error-report.h"
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#include "bootparam.h"
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#include "xtensa_memory.h"
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typedef struct XtfpgaBoardDesc {
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hwaddr flash_base;
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size_t flash_size;
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size_t flash_boot_base;
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size_t flash_sector_size;
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size_t sram_size;
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} XtfpgaBoardDesc;
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typedef struct XtfpgaFpgaState {
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MemoryRegion iomem;
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uint32_t leds;
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uint32_t switches;
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} XtfpgaFpgaState;
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static void xtfpga_fpga_reset(void *opaque)
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{
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XtfpgaFpgaState *s = opaque;
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s->leds = 0;
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s->switches = 0;
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}
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static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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XtfpgaFpgaState *s = opaque;
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switch (addr) {
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case 0x0: /*build date code*/
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return 0x09272011;
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case 0x4: /*processor clock frequency, Hz*/
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return 10000000;
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case 0x8: /*LEDs (off = 0, on = 1)*/
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return s->leds;
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case 0xc: /*DIP switches (off = 0, on = 1)*/
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return s->switches;
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}
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return 0;
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}
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static void xtfpga_fpga_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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XtfpgaFpgaState *s = opaque;
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switch (addr) {
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case 0x8: /*LEDs (off = 0, on = 1)*/
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s->leds = val;
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break;
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case 0x10: /*board reset*/
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if (val == 0xdead) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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}
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break;
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}
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}
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static const MemoryRegionOps xtfpga_fpga_ops = {
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.read = xtfpga_fpga_read,
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.write = xtfpga_fpga_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
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hwaddr base)
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{
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XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState));
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memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
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"xtfpga.fpga", 0x10000);
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memory_region_add_subregion(address_space, base, &s->iomem);
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xtfpga_fpga_reset(s);
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qemu_register_reset(xtfpga_fpga_reset, s);
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return s;
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}
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static void xtfpga_net_init(MemoryRegion *address_space,
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hwaddr base,
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hwaddr descriptors,
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hwaddr buffers,
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qemu_irq irq, NICInfo *nd)
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{
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DeviceState *dev;
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SysBusDevice *s;
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MemoryRegion *ram;
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dev = qdev_create(NULL, "open_eth");
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qdev_set_nic_properties(dev, nd);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_connect_irq(s, 0, irq);
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memory_region_add_subregion(address_space, base,
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sysbus_mmio_get_region(s, 0));
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memory_region_add_subregion(address_space, descriptors,
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sysbus_mmio_get_region(s, 1));
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ram = g_malloc(sizeof(*ram));
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memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16384,
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&error_fatal);
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vmstate_register_ram_global(ram);
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memory_region_add_subregion(address_space, buffers, ram);
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}
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static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
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const XtfpgaBoardDesc *board,
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DriveInfo *dinfo, int be)
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{
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SysBusDevice *s;
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DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
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qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
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&error_abort);
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qdev_prop_set_uint32(dev, "num-blocks",
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board->flash_size / board->flash_sector_size);
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qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size);
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qdev_prop_set_uint8(dev, "width", 2);
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qdev_prop_set_bit(dev, "big-endian", be);
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qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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memory_region_add_subregion(address_space, board->flash_base,
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sysbus_mmio_get_region(s, 0));
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return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
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}
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static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
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{
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XtensaCPU *cpu = opaque;
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return cpu_get_phys_page_debug(CPU(cpu), addr);
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}
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static void xtfpga_reset(void *opaque)
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{
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XtensaCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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}
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static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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return 0;
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}
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static void xtfpga_io_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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}
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static const MemoryRegionOps xtfpga_io_ops = {
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.read = xtfpga_io_read,
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.write = xtfpga_io_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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int be = 1;
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#else
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int be = 0;
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#endif
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MemoryRegion *system_memory = get_system_memory();
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XtensaCPU *cpu = NULL;
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CPUXtensaState *env = NULL;
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MemoryRegion *system_io;
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DriveInfo *dinfo;
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pflash_t *flash = NULL;
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QemuOpts *machine_opts = qemu_get_machine_opts();
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const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
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const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
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const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
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const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
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int n;
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for (n = 0; n < smp_cpus; n++) {
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cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
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env = &cpu->env;
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env->sregs[PRID] = n;
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qemu_register_reset(xtfpga_reset, cpu);
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/* Need MMU initialized prior to ELF loading,
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* so that ELF gets loaded into virtual addresses
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*/
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cpu_reset(CPU(cpu));
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}
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if (env) {
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XtensaMemory sysram = env->config->sysram;
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sysram.location[0].size = machine->ram_size;
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xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
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system_memory);
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xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
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system_memory);
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xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
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system_memory);
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xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
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system_memory);
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xtensa_create_memory_regions(&sysram, "xtensa.sysram",
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system_memory);
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}
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system_io = g_malloc(sizeof(*system_io));
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memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
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224 * 1024 * 1024);
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memory_region_add_subregion(system_memory, 0xf0000000, system_io);
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xtfpga_fpga_init(system_io, 0x0d020000);
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if (nd_table[0].used) {
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xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
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xtensa_get_extint(env, 1), nd_table);
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}
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if (!serial_hds[0]) {
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serial_hds[0] = qemu_chr_new("serial0", "null");
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}
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serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
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115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
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dinfo = drive_get(IF_PFLASH, 0, 0);
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if (dinfo) {
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flash = xtfpga_flash_init(system_io, board, dinfo, be);
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}
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/* Use presence of kernel file name as 'boot from SRAM' switch. */
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if (kernel_filename) {
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uint32_t entry_point = env->pc;
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size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
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uint32_t tagptr = env->config->sysrom.location[0].addr +
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board->sram_size;
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uint32_t cur_tagptr;
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BpMemInfo memory_location = {
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.type = tswap32(MEMORY_TYPE_CONVENTIONAL),
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.start = tswap32(env->config->sysram.location[0].addr),
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.end = tswap32(env->config->sysram.location[0].addr +
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machine->ram_size),
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};
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uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
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machine->ram_size : 0x08000000;
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uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
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lowmem_end += env->config->sysram.location[0].addr;
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cur_lowmem += env->config->sysram.location[0].addr;
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xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
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system_memory);
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if (kernel_cmdline) {
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bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
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}
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if (dtb_filename) {
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bp_size += get_tag_size(sizeof(uint32_t));
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}
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if (initrd_filename) {
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bp_size += get_tag_size(sizeof(BpMemInfo));
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}
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/* Put kernel bootparameters to the end of that SRAM */
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tagptr = (tagptr - bp_size) & ~0xff;
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cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
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cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
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sizeof(memory_location), &memory_location);
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if (kernel_cmdline) {
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cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
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strlen(kernel_cmdline) + 1, kernel_cmdline);
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}
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#ifdef CONFIG_FDT
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if (dtb_filename) {
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int fdt_size;
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void *fdt = load_device_tree(dtb_filename, &fdt_size);
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uint32_t dtb_addr = tswap32(cur_lowmem);
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if (!fdt) {
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error_report("could not load DTB '%s'", dtb_filename);
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exit(EXIT_FAILURE);
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}
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cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
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cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
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sizeof(dtb_addr), &dtb_addr);
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cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096);
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}
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#else
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if (dtb_filename) {
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error_report("could not load DTB '%s': "
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"FDT support is not configured in QEMU",
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dtb_filename);
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exit(EXIT_FAILURE);
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}
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#endif
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if (initrd_filename) {
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BpMemInfo initrd_location = { 0 };
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int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
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lowmem_end - cur_lowmem);
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if (initrd_size < 0) {
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initrd_size = load_image_targphys(initrd_filename,
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cur_lowmem,
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lowmem_end - cur_lowmem);
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}
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if (initrd_size < 0) {
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error_report("could not load initrd '%s'", initrd_filename);
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exit(EXIT_FAILURE);
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}
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initrd_location.start = tswap32(cur_lowmem);
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initrd_location.end = tswap32(cur_lowmem + initrd_size);
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cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
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sizeof(initrd_location), &initrd_location);
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cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096);
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}
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cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
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env->regs[2] = tagptr;
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uint64_t elf_entry;
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uint64_t elf_lowaddr;
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int success = load_elf(kernel_filename, translate_phys_addr, cpu,
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&elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0);
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if (success > 0) {
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entry_point = elf_entry;
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} else {
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hwaddr ep;
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int is_linux;
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success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
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translate_phys_addr, cpu);
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if (success > 0 && is_linux) {
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entry_point = ep;
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} else {
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error_report("could not load kernel '%s'",
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kernel_filename);
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exit(EXIT_FAILURE);
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}
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}
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if (entry_point != env->pc) {
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uint8_t boot[] = {
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#ifdef TARGET_WORDS_BIGENDIAN
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0x60, 0x00, 0x08, /* j 1f */
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0x00, /* .literal_position */
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0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
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0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
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/* 1: */
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0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
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0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
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0x0a, 0x00, 0x00, /* jx a0 */
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#else
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0x06, 0x02, 0x00, /* j 1f */
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0x00, /* .literal_position */
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0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
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0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
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/* 1: */
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0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
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0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
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0xa0, 0x00, 0x00, /* jx a0 */
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#endif
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};
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uint32_t entry_pc = tswap32(entry_point);
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uint32_t entry_a2 = tswap32(tagptr);
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memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
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memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
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cpu_physical_memory_write(env->pc, boot, sizeof(boot));
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}
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} else {
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if (flash) {
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MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
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MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
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uint32_t size = env->config->sysrom.location[0].size;
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if (board->flash_size - board->flash_boot_base < size) {
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size = board->flash_size - board->flash_boot_base;
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}
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memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
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flash_mr, board->flash_boot_base, size);
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memory_region_add_subregion(system_memory,
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env->config->sysrom.location[0].addr,
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flash_io);
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} else {
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xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
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system_memory);
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}
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}
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}
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static void xtfpga_lx60_init(MachineState *machine)
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{
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static const XtfpgaBoardDesc lx60_board = {
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.flash_base = 0x08000000,
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.flash_size = 0x00400000,
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.flash_sector_size = 0x10000,
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.sram_size = 0x20000,
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};
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xtfpga_init(&lx60_board, machine);
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}
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static void xtfpga_lx200_init(MachineState *machine)
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{
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static const XtfpgaBoardDesc lx200_board = {
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.flash_base = 0x08000000,
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.flash_size = 0x01000000,
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.flash_sector_size = 0x20000,
|
|
.sram_size = 0x2000000,
|
|
};
|
|
xtfpga_init(&lx200_board, machine);
|
|
}
|
|
|
|
static void xtfpga_ml605_init(MachineState *machine)
|
|
{
|
|
static const XtfpgaBoardDesc ml605_board = {
|
|
.flash_base = 0x08000000,
|
|
.flash_size = 0x01000000,
|
|
.flash_sector_size = 0x20000,
|
|
.sram_size = 0x2000000,
|
|
};
|
|
xtfpga_init(&ml605_board, machine);
|
|
}
|
|
|
|
static void xtfpga_kc705_init(MachineState *machine)
|
|
{
|
|
static const XtfpgaBoardDesc kc705_board = {
|
|
.flash_base = 0x00000000,
|
|
.flash_size = 0x08000000,
|
|
.flash_boot_base = 0x06000000,
|
|
.flash_sector_size = 0x20000,
|
|
.sram_size = 0x2000000,
|
|
};
|
|
xtfpga_init(&kc705_board, machine);
|
|
}
|
|
|
|
static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
|
mc->init = xtfpga_lx60_init;
|
|
mc->max_cpus = 4;
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
|
}
|
|
|
|
static const TypeInfo xtfpga_lx60_type = {
|
|
.name = MACHINE_TYPE_NAME("lx60"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = xtfpga_lx60_class_init,
|
|
};
|
|
|
|
static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
|
mc->init = xtfpga_lx200_init;
|
|
mc->max_cpus = 4;
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
|
}
|
|
|
|
static const TypeInfo xtfpga_lx200_type = {
|
|
.name = MACHINE_TYPE_NAME("lx200"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = xtfpga_lx200_class_init,
|
|
};
|
|
|
|
static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
|
mc->init = xtfpga_ml605_init;
|
|
mc->max_cpus = 4;
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
|
}
|
|
|
|
static const TypeInfo xtfpga_ml605_type = {
|
|
.name = MACHINE_TYPE_NAME("ml605"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = xtfpga_ml605_class_init,
|
|
};
|
|
|
|
static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
|
|
mc->init = xtfpga_kc705_init;
|
|
mc->max_cpus = 4;
|
|
mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
|
|
}
|
|
|
|
static const TypeInfo xtfpga_kc705_type = {
|
|
.name = MACHINE_TYPE_NAME("kc705"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = xtfpga_kc705_class_init,
|
|
};
|
|
|
|
static void xtfpga_machines_init(void)
|
|
{
|
|
type_register_static(&xtfpga_lx60_type);
|
|
type_register_static(&xtfpga_lx200_type);
|
|
type_register_static(&xtfpga_ml605_type);
|
|
type_register_static(&xtfpga_kc705_type);
|
|
}
|
|
|
|
type_init(xtfpga_machines_init)
|