ba6a4fd95d
KVM recently gained support for Hyper-V Reenlightenment MSRs which are required to make KVM-on-Hyper-V enable TSC page clocksource to its guests when INVTSC is not passed to it (and it is not passed by default in Qemu as it effectively blocks migration). Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20180411115036.31832-2-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
268 lines
8.9 KiB
C
268 lines
8.9 KiB
C
/*
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* Definitions for Hyper-V guest/hypervisor interaction
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*
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* Copyright (C) 2017 Parallels International GmbH
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef TARGET_I386_HYPERV_PROTO_H
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#define TARGET_I386_HYPERV_PROTO_H
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#include "qemu/bitmap.h"
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#define HV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
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#define HV_CPUID_INTERFACE 0x40000001
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#define HV_CPUID_VERSION 0x40000002
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#define HV_CPUID_FEATURES 0x40000003
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#define HV_CPUID_ENLIGHTMENT_INFO 0x40000004
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#define HV_CPUID_IMPLEMENT_LIMITS 0x40000005
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#define HV_CPUID_MIN 0x40000005
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#define HV_CPUID_MAX 0x4000ffff
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#define HV_HYPERVISOR_PRESENT_BIT 0x80000000
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/*
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* HV_CPUID_FEATURES.EAX bits
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*/
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#define HV_VP_RUNTIME_AVAILABLE (1u << 0)
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#define HV_TIME_REF_COUNT_AVAILABLE (1u << 1)
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#define HV_SYNIC_AVAILABLE (1u << 2)
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#define HV_SYNTIMERS_AVAILABLE (1u << 3)
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#define HV_APIC_ACCESS_AVAILABLE (1u << 4)
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#define HV_HYPERCALL_AVAILABLE (1u << 5)
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#define HV_VP_INDEX_AVAILABLE (1u << 6)
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#define HV_RESET_AVAILABLE (1u << 7)
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#define HV_REFERENCE_TSC_AVAILABLE (1u << 9)
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#define HV_ACCESS_FREQUENCY_MSRS (1u << 11)
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#define HV_ACCESS_REENLIGHTENMENTS_CONTROL (1u << 13)
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/*
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* HV_CPUID_FEATURES.EDX bits
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*/
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#define HV_MWAIT_AVAILABLE (1u << 0)
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#define HV_GUEST_DEBUGGING_AVAILABLE (1u << 1)
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#define HV_PERF_MONITOR_AVAILABLE (1u << 2)
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#define HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1u << 3)
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#define HV_HYPERCALL_PARAMS_XMM_AVAILABLE (1u << 4)
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#define HV_GUEST_IDLE_STATE_AVAILABLE (1u << 5)
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#define HV_FREQUENCY_MSRS_AVAILABLE (1u << 8)
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#define HV_GUEST_CRASH_MSR_AVAILABLE (1u << 10)
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/*
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* HV_CPUID_ENLIGHTMENT_INFO.EAX bits
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*/
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#define HV_AS_SWITCH_RECOMMENDED (1u << 0)
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#define HV_LOCAL_TLB_FLUSH_RECOMMENDED (1u << 1)
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#define HV_REMOTE_TLB_FLUSH_RECOMMENDED (1u << 2)
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#define HV_APIC_ACCESS_RECOMMENDED (1u << 3)
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#define HV_SYSTEM_RESET_RECOMMENDED (1u << 4)
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#define HV_RELAXED_TIMING_RECOMMENDED (1u << 5)
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/*
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* Basic virtualized MSRs
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*/
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#define HV_X64_MSR_GUEST_OS_ID 0x40000000
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#define HV_X64_MSR_HYPERCALL 0x40000001
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#define HV_X64_MSR_VP_INDEX 0x40000002
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#define HV_X64_MSR_RESET 0x40000003
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#define HV_X64_MSR_VP_RUNTIME 0x40000010
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#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
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#define HV_X64_MSR_REFERENCE_TSC 0x40000021
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#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
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#define HV_X64_MSR_APIC_FREQUENCY 0x40000023
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/*
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* Virtual APIC MSRs
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*/
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#define HV_X64_MSR_EOI 0x40000070
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#define HV_X64_MSR_ICR 0x40000071
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#define HV_X64_MSR_TPR 0x40000072
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#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073
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/*
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* Synthetic interrupt controller MSRs
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*/
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#define HV_X64_MSR_SCONTROL 0x40000080
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#define HV_X64_MSR_SVERSION 0x40000081
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#define HV_X64_MSR_SIEFP 0x40000082
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#define HV_X64_MSR_SIMP 0x40000083
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#define HV_X64_MSR_EOM 0x40000084
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#define HV_X64_MSR_SINT0 0x40000090
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#define HV_X64_MSR_SINT1 0x40000091
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#define HV_X64_MSR_SINT2 0x40000092
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#define HV_X64_MSR_SINT3 0x40000093
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#define HV_X64_MSR_SINT4 0x40000094
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#define HV_X64_MSR_SINT5 0x40000095
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#define HV_X64_MSR_SINT6 0x40000096
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#define HV_X64_MSR_SINT7 0x40000097
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#define HV_X64_MSR_SINT8 0x40000098
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#define HV_X64_MSR_SINT9 0x40000099
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#define HV_X64_MSR_SINT10 0x4000009A
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#define HV_X64_MSR_SINT11 0x4000009B
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#define HV_X64_MSR_SINT12 0x4000009C
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#define HV_X64_MSR_SINT13 0x4000009D
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#define HV_X64_MSR_SINT14 0x4000009E
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#define HV_X64_MSR_SINT15 0x4000009F
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/*
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* Synthetic timer MSRs
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*/
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#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0
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#define HV_X64_MSR_STIMER0_COUNT 0x400000B1
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#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2
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#define HV_X64_MSR_STIMER1_COUNT 0x400000B3
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#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4
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#define HV_X64_MSR_STIMER2_COUNT 0x400000B5
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#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
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#define HV_X64_MSR_STIMER3_COUNT 0x400000B7
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/*
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* Guest crash notification MSRs
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*/
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#define HV_X64_MSR_CRASH_P0 0x40000100
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#define HV_X64_MSR_CRASH_P1 0x40000101
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#define HV_X64_MSR_CRASH_P2 0x40000102
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#define HV_X64_MSR_CRASH_P3 0x40000103
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#define HV_X64_MSR_CRASH_P4 0x40000104
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#define HV_CRASH_PARAMS (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0 + 1)
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#define HV_X64_MSR_CRASH_CTL 0x40000105
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#define HV_CRASH_CTL_NOTIFY (1ull << 63)
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/*
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* Reenlightenment notification MSRs
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*/
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#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
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#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
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#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
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/*
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* Hypercall status code
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*/
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#define HV_STATUS_SUCCESS 0
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#define HV_STATUS_INVALID_HYPERCALL_CODE 2
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#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
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#define HV_STATUS_INVALID_ALIGNMENT 4
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#define HV_STATUS_INVALID_PARAMETER 5
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#define HV_STATUS_INSUFFICIENT_MEMORY 11
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#define HV_STATUS_INVALID_CONNECTION_ID 18
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#define HV_STATUS_INSUFFICIENT_BUFFERS 19
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/*
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* Hypercall numbers
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*/
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#define HV_POST_MESSAGE 0x005c
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#define HV_SIGNAL_EVENT 0x005d
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#define HV_HYPERCALL_FAST (1u << 16)
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/*
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* Hypercall MSR bits
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*/
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#define HV_HYPERCALL_ENABLE (1u << 0)
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/*
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* Synthetic interrupt controller definitions
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*/
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#define HV_SYNIC_VERSION 1
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#define HV_SINT_COUNT 16
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#define HV_SYNIC_ENABLE (1u << 0)
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#define HV_SIMP_ENABLE (1u << 0)
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#define HV_SIEFP_ENABLE (1u << 0)
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#define HV_SINT_MASKED (1u << 16)
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#define HV_SINT_AUTO_EOI (1u << 17)
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#define HV_SINT_VECTOR_MASK 0xff
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#define HV_STIMER_COUNT 4
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/*
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* Message size
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*/
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#define HV_MESSAGE_PAYLOAD_SIZE 240
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/*
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* Message types
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*/
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#define HV_MESSAGE_NONE 0x00000000
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#define HV_MESSAGE_VMBUS 0x00000001
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#define HV_MESSAGE_UNMAPPED_GPA 0x80000000
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#define HV_MESSAGE_GPA_INTERCEPT 0x80000001
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#define HV_MESSAGE_TIMER_EXPIRED 0x80000010
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#define HV_MESSAGE_INVALID_VP_REGISTER_VALUE 0x80000020
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#define HV_MESSAGE_UNRECOVERABLE_EXCEPTION 0x80000021
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#define HV_MESSAGE_UNSUPPORTED_FEATURE 0x80000022
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#define HV_MESSAGE_EVENTLOG_BUFFERCOMPLETE 0x80000040
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#define HV_MESSAGE_X64_IOPORT_INTERCEPT 0x80010000
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#define HV_MESSAGE_X64_MSR_INTERCEPT 0x80010001
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#define HV_MESSAGE_X64_CPUID_INTERCEPT 0x80010002
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#define HV_MESSAGE_X64_EXCEPTION_INTERCEPT 0x80010003
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#define HV_MESSAGE_X64_APIC_EOI 0x80010004
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#define HV_MESSAGE_X64_LEGACY_FP_ERROR 0x80010005
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/*
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* Message flags
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*/
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#define HV_MESSAGE_FLAG_PENDING 0x1
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/*
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* Event flags number per SINT
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*/
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#define HV_EVENT_FLAGS_COUNT (256 * 8)
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/*
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* Connection id valid bits
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*/
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#define HV_CONNECTION_ID_MASK 0x00ffffff
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/*
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* Input structure for POST_MESSAGE hypercall
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*/
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struct hyperv_post_message_input {
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uint32_t connection_id;
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uint32_t _reserved;
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uint32_t message_type;
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uint32_t payload_size;
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uint8_t payload[HV_MESSAGE_PAYLOAD_SIZE];
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};
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/*
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* Input structure for SIGNAL_EVENT hypercall
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*/
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struct hyperv_signal_event_input {
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uint32_t connection_id;
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uint16_t flag_number;
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uint16_t _reserved_zero;
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};
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/*
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* SynIC message structures
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*/
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struct hyperv_message_header {
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uint32_t message_type;
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uint8_t payload_size;
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uint8_t message_flags; /* HV_MESSAGE_FLAG_XX */
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uint8_t _reserved[2];
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uint64_t sender;
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};
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struct hyperv_message {
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struct hyperv_message_header header;
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uint8_t payload[HV_MESSAGE_PAYLOAD_SIZE];
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};
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struct hyperv_message_page {
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struct hyperv_message slot[HV_SINT_COUNT];
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};
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/*
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* SynIC event flags structures
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*/
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struct hyperv_event_flags {
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DECLARE_BITMAP(flags, HV_EVENT_FLAGS_COUNT);
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};
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struct hyperv_event_flags_page {
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struct hyperv_event_flags slot[HV_SINT_COUNT];
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};
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#endif
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