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e494cd0a1a
qemu/target/arm
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Peter Maydell e494cd0a1a target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access 
A few subcases of VLDR/VSTR sysreg succeed but do not perform a
memory access:
 * VSTR of VPR when unprivileged
 * VLDR to VPR when unprivileged
 * VLDR to FPCXT_NS when fpInactive

In these cases, even though we don't do the memory access we should
still update the base register and perform the stack limit check if
the insn's addressing mode specifies writeback.  Our implementation
failed to do this, because we handle these side-effects inside the
memory_to_fp_sysreg() and fp_sysreg_to_memory() callback functions,
which are only called if there's something to load or store.

Fix this by adding an extra argument to the callbacks which is set to
true to actually perform the access and false to only do side effects
like writeback, and calling the callback with do_access = false
for the three cases listed above.

This produces slightly suboptimal code for the case of a write
to FPCXT_NS when the FPU is inactive and the insn didn't have
side effects (ie no writeback, or via VMSR), in which case we'll
generate a conditional branch over an unconditional branch.
But this doesn't seem to be important enough to merit requiring
the callback to report back whether it generated any code or not.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210618141019.10671-5-peter.maydell@linaro.org
2021-06-21 16:49:37 +01:00
..
a32-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
a32.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
arch_dump.c target/arm: add spaces around operator 2020-11-10 11:03:47 +00:00
arm_ldst.h arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
arm-powerctl.c arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() 2019-12-20 14:03:00 +00:00
arm-powerctl.h target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset() 2019-02-28 11:03:04 +00:00
cpu64.c target/arm: Enable BFloat16 extensions 2021-06-03 16:43:26 +01:00
cpu_tcg.c target/arm: Enable BFloat16 extensions 2021-06-03 16:43:26 +01:00
cpu-param.h linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE 2021-02-16 13:06:16 +00:00
cpu-qom.h qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros 2020-09-18 14:12:32 -04:00
cpu.c target/arm: Enable BFloat16 extensions 2021-06-03 16:43:26 +01:00
cpu.h target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16 2021-06-03 16:43:25 +01:00
crypto_helper.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
debug_helper.c target/arm: Stop assuming DBGDIDR always exists 2020-02-21 16:07:01 +00:00
gdbstub64.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
gdbstub.c target/arm: use official org.gnu.gdb.aarch64.sve layout for registers 2021-01-18 10:05:06 +00:00
helper-a64.c target/arm: Add wrapper macros for accessing tbflags 2021-04-30 11:16:50 +01:00
helper-a64.h target/arm: Merge mte_check1, mte_checkN 2021-04-30 11:16:49 +01:00
helper-sve.h target/arm: Implement vector float32 to bfloat16 conversion 2021-06-03 16:43:26 +01:00
helper.c target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 2021-05-25 16:01:43 +01:00
helper.h target/arm: Implement bfloat widening fma (indexed) 2021-06-03 16:43:26 +01:00
idau.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
internals.h target/arm: Rename mte_probe1 to mte_probe 2021-04-30 11:16:49 +01:00
iwmmxt_helper.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
kvm64.c target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors 2021-06-21 16:49:37 +01:00
kvm_arm.h hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
kvm-consts.h target/arm: Remove no-longer-reachable 32-bit KVM code 2020-09-14 14:23:19 +01:00
kvm-stub.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
kvm.c hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
m_helper.c target/arm: Handle VPR semantics in existing code 2021-06-16 14:33:52 +01:00
m-nocp.decode target/arm: Don't NOCP fault for FPCXT_NS accesses 2021-06-21 16:49:37 +01:00
machine.c target/arm: Make FPSCR.LTPSIZE writable for MVE 2021-06-03 16:43:25 +01:00
meson.build target/arm: Add framework for MVE decode 2021-06-16 14:33:52 +01:00
monitor.c target/arm: Add cpu properties to control pauth 2021-01-19 14:38:51 +00:00
mte_helper.c target/arm: Fix mte page crossing test 2021-06-16 14:33:51 +01:00
mve.decode target/arm: Add framework for MVE decode 2021-06-16 14:33:52 +01:00
neon_helper.c target/arm: Split out saturating/rounding shifts from neon 2021-05-25 16:01:43 +01:00
neon-dp.decode target/arm: Implement vector float32 to bfloat16 conversion 2021-06-03 16:43:26 +01:00
neon-ls.decode target/arm: Fix decode of align in VLDST_single 2021-04-30 11:16:49 +01:00
neon-shared.decode target/arm: Implement bfloat widening fma (indexed) 2021-06-03 16:43:26 +01:00
op_addsub.h
op_helper.c target/arm: use raise_exception_ra for stack limit exception 2021-06-03 16:43:25 +01:00
pauth_helper.c target/arm: Implement an IMPDEF pauth algorithm 2021-01-19 14:38:51 +00:00
psci.c sysemu: Split sysemu/runstate.h off sysemu/sysemu.h 2019-08-16 13:37:36 +02:00
sve_helper.c bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations 2021-06-16 14:33:52 +01:00
sve.decode target/arm: Implement bfloat widening fma (indexed) 2021-06-03 16:43:26 +01:00
syndrome.h target/arm: Split out syndrome.h from internals.h 2021-02-16 13:16:18 +00:00
t16.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
t32.decode target/arm: Implement MVE LETP insn 2021-06-16 14:33:52 +01:00
tlb_helper.c target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill 2021-03-23 14:07:55 +00:00
trace-events docs: fix references to docs/devel/tracing.rst 2021-06-02 06:51:09 +02:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate-a32.h target/arm: Don't NOCP fault for FPCXT_NS accesses 2021-06-21 16:49:37 +01:00
translate-a64.c target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16 2021-06-15 16:18:48 +01:00
translate-a64.h target/arm: Implement SVE2 XAR 2021-05-25 16:01:44 +01:00
translate-m-nocp.c target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access 2021-06-21 16:49:37 +01:00
translate-mve.c target/arm: Add framework for MVE decode 2021-06-16 14:33:52 +01:00
translate-neon.c target/arm: Implement bfloat widening fma (indexed) 2021-06-03 16:43:26 +01:00
translate-sve.c target/arm: Implement bfloat widening fma (indexed) 2021-06-03 16:43:26 +01:00
translate-vfp.c target/arm: Don't NOCP fault for FPCXT_NS accesses 2021-06-21 16:49:37 +01:00
translate.c target/arm: Add framework for MVE decode 2021-06-16 14:33:52 +01:00
translate.h target/arm: Add handling for PSR.ECI/ICI 2021-06-16 14:33:52 +01:00
vec_helper.c target/arm: Move expand_pred_b() data to vec_helper.c 2021-06-16 14:33:52 +01:00
vec_internal.h target/arm: Move expand_pred_b() data to vec_helper.c 2021-06-16 14:33:52 +01:00
vfp_helper.c target/arm: Enable FPSCR.QC bit for MVE 2021-06-16 14:33:52 +01:00
vfp-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
vfp.decode target/arm: Don't NOCP fault for FPCXT_NS accesses 2021-06-21 16:49:37 +01:00