qemu/target/riscv
Richard Henderson 597f9b2d30 accel/tcg: Pass max_insn to gen_intermediate_code by pointer
In preparation for returning the number of insns generated
via the same pointer.  Adjust only the prototypes so far.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01 07:33:27 -10:00
..
insn_trans target/riscv: fix ctzw behavior 2023-02-07 08:19:23 +10:00
arch_dump.c dump: Replace opaque DumpState pointer with a typed one 2022-10-06 19:30:43 +04:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: Add smstateen support 2023-01-06 10:42:55 +10:00
cpu_helper.c target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state() 2023-02-23 14:21:33 -08:00
cpu_user.h
cpu_vendorid.h RISC-V: Add initial support for T-Head C906 2023-02-07 08:19:23 +10:00
cpu-param.h
cpu.c target/riscv: Replace tb_pc() with tb->pc 2023-03-01 07:33:14 -10:00
cpu.h target/riscv/cpu: Move Floating-Point fields closer 2023-02-27 22:29:01 +01:00
crypto_helper.c
csr.c target/riscv: Remove privileged spec version restriction for RVV 2023-02-23 14:21:31 -08:00
debug.c target/riscv: set tval for triggered watchpoints 2023-02-07 08:19:23 +10:00
debug.h target/riscv: Add itrigger support when icount is enabled 2023-01-06 10:42:55 +10:00
fpu_helper.c target/riscv: Remove helper_set_rod_rounding_mode 2023-01-20 10:14:14 +10:00
gdbstub.c target/riscv: Check the correct exception cause in vector GDB stub 2022-09-27 07:04:38 +10:00
helper.h RISC-V: Adding XTheadSync ISA extension 2023-02-07 08:19:23 +10:00
insn16.decode
insn32.decode RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
instmap.h
internals.h
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c target/riscv: fix SBI getchar handler for KVM 2023-02-07 08:19:23 +10:00
m128_helper.c
machine.c hw/char: riscv_htif: Move registers from CPUArchState to HTIFState 2023-01-20 10:14:13 +10:00
meson.build RISC-V: Adding XTheadCmo ISA extension 2023-02-07 08:19:23 +10:00
monitor.c bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx 2023-01-18 11:14:34 +01:00
op_helper.c RISC-V: Adding XTheadSync ISA extension 2023-02-07 08:19:23 +10:00
pmp.c target/riscv: Smepmp: Skip applying default rules when address matches 2023-02-23 14:21:32 -08:00
pmp.h target/riscv: Fix PMP propagation for tlb 2023-01-06 10:42:55 +10:00
pmu.c hw/riscv: virt: Add PMU DT node to the device tree 2022-09-07 09:19:15 +02:00
pmu.h riscv: Clean up includes 2023-02-08 07:28:05 +01:00
sbi_ecall_interface.h
time_helper.c target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX 2023-02-07 08:19:23 +10:00
time_helper.h target/riscv: Add stimecmp support 2022-09-07 09:19:15 +02:00
trace-events
trace.h
translate.c accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
vector_helper.c target/riscv: Fix vslide1up.vf and vslide1down.vf 2023-02-23 14:21:34 -08:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode