29318db133
SPI controller device model supports a connection to a single SPI responder. This provide access to SPI seeproms, TPM, flash device and an ADC controller. All SPI function control is mapped into the SPI register space to enable full control by firmware. In this commit SPI configuration component is modelled which contains all SPI configuration and status registers as well as the hold registers for data to be sent or having been received. An existing QEMU SSI framework is used and SSI_BUS is created. Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> [np: Fix FDT macro compile for qtest] Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
31 lines
319 B
Plaintext
31 lines
319 B
Plaintext
config PL022
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bool
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select SSI
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config SIFIVE_SPI
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bool
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select SSI
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config SSI
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bool
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config XILINX_SPI
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bool
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select SSI
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config XILINX_SPIPS
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bool
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select SSI
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config STM32F2XX_SPI
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bool
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select SSI
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config BCM2835_SPI
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bool
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select SSI
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config PNV_SPI
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bool
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select SSI
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