Fabian Aggeler e389be1673 target-arm: implement PD0/PD1 bits for TTBCR ...

Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).

Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
get_level1_table_address.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Message-id: 1402409556-18574-1-git-send-email-aggelerf@ethz.ch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2014-06-19 18:06:24 +01:00

..

arm_ldst.h

softmmu: introduce cpu_ldst.h

2014-06-05 16:10:33 +02:00

arm-semi.c

…

cpu64.c

target-arm: VFPv4 implies half-precision extension

2014-06-09 16:06:11 +01:00

cpu-qom.h

…

cpu.c

target-arm: VFPv4 implies half-precision extension

2014-06-09 16:06:11 +01:00

cpu.h

target-arm: implement PD0/PD1 bits for TTBCR

2014-06-19 18:06:24 +01:00

crypto_helper.c

target-arm: Use Common Tables in AES Instructions

2014-06-16 13:24:33 +02:00

gdbstub64.c

…

gdbstub.c

…

helper-a64.c

target-arm: A64: Implement CRC instructions

2014-06-09 16:06:12 +01:00

helper-a64.h

target-arm: A64: Implement CRC instructions

2014-06-09 16:06:12 +01:00

helper.c

target-arm: implement PD0/PD1 bits for TTBCR

2014-06-19 18:06:24 +01:00

helper.h

target-arm: Delete unused iwmmxt_msadb helper

2014-06-09 16:06:12 +01:00

internals.h

target-arm: A64: Generalize update_spsel for the various ELs

2014-05-27 17:09:54 +01:00

iwmmxt_helper.c

target-arm: Delete unused iwmmxt_msadb helper

2014-06-09 16:06:12 +01:00

kvm32.c

…

kvm64.c

…

kvm_arm.h

…

kvm-consts.h

…

kvm-stub.c

…

kvm.c

…

machine.c

…

Makefile.objs

…

neon_helper.c

target-arm: add support for v8 VMULL.P64 instruction

2014-06-09 16:06:11 +01:00

op_addsub.h

…

op_helper.c

softmmu: introduce cpu_ldst.h

2014-06-05 16:10:33 +02:00

translate-a64.c

target-arm: A64: Implement two-register SHA instructions

2014-06-09 16:06:12 +01:00

translate.c

target-arm: Delete unused iwmmxt_msadb helper

2014-06-09 16:06:12 +01:00

translate.h

…