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Yifei Jiang dbd3ec548a target/riscv: Add sifive_plic vmstate 
Add sifive_plic vmstate for supporting sifive_plic migration.
Current vmstate framework only supports one structure parameter
as num field to describe variable length arrays, so introduce
num_enables.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-7-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-11-03 07:17:23 -08:00
..
allwinner-a10-pic.c
…
apic_common.c
…
apic.c
Use DECLARE_*CHECKER* when possible (--force mode)
2020-09-09 09:27:11 -04:00
arm_gic_common.c
…
arm_gic_kvm.c
Use DECLARE_*CHECKER* when possible (--force mode)
2020-09-09 09:27:11 -04:00
arm_gic.c
…
arm_gicv2m.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
arm_gicv3_common.c
…
arm_gicv3_cpuif.c
hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
2020-11-02 16:52:17 +00:00
arm_gicv3_dist.c
…
arm_gicv3_its_common.c
…
arm_gicv3_its_kvm.c
Use DECLARE_*CHECKER* when possible (--force mode)
2020-09-09 09:27:11 -04:00
arm_gicv3_kvm.c
Use DECLARE_*CHECKER* when possible (--force mode)
2020-09-09 09:27:11 -04:00
arm_gicv3_redist.c
…
arm_gicv3.c
…
armv7m_nvic.c
hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
2020-10-01 15:31:00 +01:00
aspeed_vic.c
…
bcm2835_ic.c
hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
2020-10-20 16:12:00 +01:00
bcm2836_control.c
hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
2020-10-20 16:12:00 +01:00
etraxfs_pic.c
Use DECLARE_*CHECKER* macros
2020-09-09 09:27:09 -04:00
exynos4210_combiner.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
exynos4210_gic.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
gic_internal.h
…
gicv3_internal.h
…
grlib_irqmp.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
heathrow_pic.c
…
i8259_common.c
…
i8259.c
Use DECLARE_*CHECKER* macros
2020-09-09 09:27:09 -04:00
ibex_plic.c
hw/intc: ibex_plic: Honour source priorities
2020-08-21 22:37:55 -07:00
imx_avic.c
…
imx_gpcv2.c
…
intc.c
…
ioapic_common.c
…
ioapic.c
…
Kconfig
hw/riscv: Move sifive_plic model to hw/intc
2020-09-09 15:54:19 -07:00
lm32_pic.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
loongson_liointc.c
Use DECLARE_*CHECKER* macros
2020-09-09 09:27:09 -04:00
meson.build
hw/riscv: Move sifive_plic model to hw/intc
2020-09-09 15:54:19 -07:00
mips_gic.c
…
nios2_iic.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
omap_intc.c
omap_intc: Use typedef name for instance_size
2020-09-09 13:20:22 -04:00
ompic.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
openpic_kvm.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
openpic.c
…
pl190.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
pnv_xive_regs.h
…
pnv_xive.c
…
puv3_intc.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
realview_gic.c
…
rx_icu.c
qemu/atomic.h: rename atomic_ to qatomic_
2020-09-23 16:07:44 +01:00
s390_flic_kvm.c
Use DECLARE_*CHECKER* macros
2020-09-09 09:27:09 -04:00
s390_flic.c
…
sh_intc.c
…
sifive_clint.c
hw/riscv: Move sifive_clint model to hw/intc
2020-09-09 15:54:19 -07:00
sifive_plic.c
target/riscv: Add sifive_plic vmstate
2020-11-03 07:17:23 -08:00
slavio_intctl.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
spapr_xive_kvm.c
spapr/xive: Allocate vCPU IPIs from the vCPU contexts
2020-09-08 10:08:42 +10:00
spapr_xive.c
spapr/xive: Add a 'hv-prio' property to represent the KVM escalation priority
2020-09-08 10:08:42 +10:00
trace-events
hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
2020-10-20 16:12:00 +01:00
trace.h
…
vgic_common.h
…
xics_kvm.c
…
xics_pnv.c
…
xics_spapr.c
…
xics.c
…
xilinx_intc.c
Use DECLARE_*CHECKER* macros
2020-09-09 09:27:09 -04:00
xive.c
…
xlnx-pmu-iomod-intc.c
…
xlnx-zynqmp-ipi.c
…