e25c3887e6
Allow the code that tcg generates to be less obtuse, passing in the return address directly instead of computing it in the helper. Maintain the old entrance point unchanged as an alternate entry point. Delete the helper_st*_cmmu prototypes; the implementations did not exist. Signed-off-by: Richard Henderson <rth@twiddle.net>
339 lines
12 KiB
C
339 lines
12 KiB
C
/*
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* Software MMU support
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*
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* Generate helpers used by TCG for qemu_ld/st ops and code load
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* functions.
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*
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* Included from target op helpers and exec.c.
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/timer.h"
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#include "exec/memory.h"
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#define DATA_SIZE (1 << SHIFT)
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#if DATA_SIZE == 8
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#define SUFFIX q
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#define USUFFIX q
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#define DATA_TYPE uint64_t
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#elif DATA_SIZE == 4
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#define SUFFIX l
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#define USUFFIX l
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#define DATA_TYPE uint32_t
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#elif DATA_SIZE == 2
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#define SUFFIX w
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#define USUFFIX uw
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#define DATA_TYPE uint16_t
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#elif DATA_SIZE == 1
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#define SUFFIX b
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#define USUFFIX ub
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#define DATA_TYPE uint8_t
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#else
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#error unsupported data size
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#endif
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#ifdef SOFTMMU_CODE_ACCESS
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#define READ_ACCESS_TYPE 2
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#define ADDR_READ addr_code
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#else
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#define READ_ACCESS_TYPE 0
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#define ADDR_READ addr_read
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#endif
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static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr,
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int mmu_idx,
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uintptr_t retaddr);
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static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
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hwaddr physaddr,
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target_ulong addr,
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uintptr_t retaddr)
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{
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uint64_t val;
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MemoryRegion *mr = iotlb_to_region(physaddr);
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physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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env->mem_io_pc = retaddr;
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if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
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cpu_io_recompile(env, retaddr);
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}
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env->mem_io_vaddr = addr;
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io_mem_read(mr, physaddr, &val, 1 << SHIFT);
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return val;
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}
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/* handle all cases except unaligned access which span two pages */
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#ifdef SOFTMMU_CODE_ACCESS
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static
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#endif
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DATA_TYPE
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glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr, int mmu_idx,
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uintptr_t retaddr)
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{
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DATA_TYPE res;
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int index;
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target_ulong tlb_addr;
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hwaddr ioaddr;
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/* test if there is match for unaligned or IO access */
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/* XXX: could done more in memory macro in a non portable way */
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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ioaddr = env->iotlb[mmu_idx][index];
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res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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/* slow unaligned access (it spans two pages or IO) */
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do_unaligned_access:
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#ifdef ALIGNED_ONLY
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do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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#endif
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res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr,
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mmu_idx, retaddr);
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} else {
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/* unaligned/aligned access in the same page */
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uintptr_t addend;
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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}
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#endif
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addend = env->tlb_table[mmu_idx][index].addend;
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res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(intptr_t)
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(addr + addend));
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}
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} else {
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0)
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do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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#endif
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tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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goto redo;
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}
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return res;
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}
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DATA_TYPE
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glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
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int mmu_idx)
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{
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return glue(glue(helper_ret_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx,
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GETPC_EXT());
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}
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/* handle all unaligned cases */
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static DATA_TYPE
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glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr,
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int mmu_idx,
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uintptr_t retaddr)
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{
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DATA_TYPE res, res1, res2;
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int index, shift;
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hwaddr ioaddr;
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target_ulong tlb_addr, addr1, addr2;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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ioaddr = env->iotlb[mmu_idx][index];
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res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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do_unaligned_access:
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/* slow unaligned access (it spans two pages) */
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addr1 = addr & ~(DATA_SIZE - 1);
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addr2 = addr1 + DATA_SIZE;
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res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr1,
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mmu_idx, retaddr);
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res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(env, addr2,
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mmu_idx, retaddr);
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shift = (addr & (DATA_SIZE - 1)) * 8;
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#ifdef TARGET_WORDS_BIGENDIAN
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res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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#else
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res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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#endif
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res = (DATA_TYPE)res;
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} else {
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/* unaligned/aligned access in the same page */
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uintptr_t addend = env->tlb_table[mmu_idx][index].addend;
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res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(intptr_t)
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(addr + addend));
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}
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} else {
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/* the page is not in the TLB : fill it */
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tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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goto redo;
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}
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return res;
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}
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#ifndef SOFTMMU_CODE_ACCESS
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static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr,
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DATA_TYPE val,
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int mmu_idx,
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uintptr_t retaddr);
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static inline void glue(io_write, SUFFIX)(CPUArchState *env,
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hwaddr physaddr,
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DATA_TYPE val,
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target_ulong addr,
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uintptr_t retaddr)
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{
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MemoryRegion *mr = iotlb_to_region(physaddr);
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physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
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cpu_io_recompile(env, retaddr);
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}
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env->mem_io_vaddr = addr;
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env->mem_io_pc = retaddr;
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io_mem_write(mr, physaddr, val, 1 << SHIFT);
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}
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void
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glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr, DATA_TYPE val,
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int mmu_idx, uintptr_t retaddr)
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{
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hwaddr ioaddr;
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target_ulong tlb_addr;
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int index;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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ioaddr = env->iotlb[mmu_idx][index];
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glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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do_unaligned_access:
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#ifdef ALIGNED_ONLY
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do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
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#endif
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glue(glue(slow_st, SUFFIX), MMUSUFFIX)(env, addr, val,
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mmu_idx, retaddr);
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} else {
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/* aligned/unaligned access in the same page */
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uintptr_t addend;
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
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}
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#endif
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addend = env->tlb_table[mmu_idx][index].addend;
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glue(glue(st, SUFFIX), _raw)((uint8_t *)(intptr_t)
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(addr + addend), val);
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}
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} else {
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/* the page is not in the TLB : fill it */
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0)
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do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
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#endif
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tlb_fill(env, addr, 1, mmu_idx, retaddr);
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goto redo;
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}
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}
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void
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glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
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DATA_TYPE val, int mmu_idx)
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{
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glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, val, mmu_idx,
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GETPC_EXT());
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}
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/* handles all unaligned cases */
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static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr,
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DATA_TYPE val,
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int mmu_idx,
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uintptr_t retaddr)
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{
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hwaddr ioaddr;
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target_ulong tlb_addr;
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int index, i;
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index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo:
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tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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if ((addr & (DATA_SIZE - 1)) != 0)
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goto do_unaligned_access;
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ioaddr = env->iotlb[mmu_idx][index];
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glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
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} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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do_unaligned_access:
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/* XXX: not efficient, but simple */
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/* Note: relies on the fact that tlb_fill() does not remove the
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* previous page from the TLB cache. */
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for(i = DATA_SIZE - 1; i >= 0; i--) {
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#ifdef TARGET_WORDS_BIGENDIAN
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glue(slow_stb, MMUSUFFIX)(env, addr + i,
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val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
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mmu_idx, retaddr);
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#else
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glue(slow_stb, MMUSUFFIX)(env, addr + i,
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val >> (i * 8),
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mmu_idx, retaddr);
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#endif
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}
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} else {
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/* aligned/unaligned access in the same page */
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uintptr_t addend = env->tlb_table[mmu_idx][index].addend;
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glue(glue(st, SUFFIX), _raw)((uint8_t *)(intptr_t)
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(addr + addend), val);
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}
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} else {
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/* the page is not in the TLB : fill it */
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tlb_fill(env, addr, 1, mmu_idx, retaddr);
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goto redo;
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}
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}
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#endif /* !defined(SOFTMMU_CODE_ACCESS) */
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#undef READ_ACCESS_TYPE
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#undef SHIFT
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#undef DATA_TYPE
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#undef SUFFIX
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#undef USUFFIX
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#undef DATA_SIZE
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#undef ADDR_READ
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