e24dc9feb0
The operations for INDEX_op_deposit_i32 and INDEX_op_deposit_i64 are now supported and enabled by default. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
165 lines
5.3 KiB
C
165 lines
5.3 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2009, 2011 Stefan Weil
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* This code implements a TCG which does not generate machine code for some
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* real target machine but which generates virtual machine code for an
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* interpreter. Interpreted pseudo code is slow, but it works on any host.
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*
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* Some remarks might help in understanding the code:
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*
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* "target" or "TCG target" is the machine which runs the generated code.
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* This is different to the usual meaning in QEMU where "target" is the
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* emulated machine. So normally QEMU host is identical to TCG target.
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* Here the TCG target is a virtual machine, but this virtual machine must
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* use the same word size like the real machine.
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* Therefore, we need both 32 and 64 bit virtual machines (interpreter).
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*/
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#if !defined(TCG_TARGET_H)
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#define TCG_TARGET_H
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#include "config-host.h"
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#define TCG_TARGET_INTERPRETER 1
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#ifdef CONFIG_DEBUG_TCG
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/* Enable debug output. */
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#define CONFIG_DEBUG_TCG_INTERPRETER
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#endif
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#if 0 /* TCI tries to emulate a little endian host. */
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#if defined(HOST_WORDS_BIGENDIAN)
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# define TCG_TARGET_WORDS_BIGENDIAN
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#endif
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#endif
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/* Optional instructions. */
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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/* Not more than one of the next two defines must be 1. */
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_div2_i32 0
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 1
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_andc_i32 0
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_movcond_i32 0
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_deposit_i64 1
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/* Not more than one of the next two defines must be 1. */
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#define TCG_TARGET_HAS_div_i64 0
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#define TCG_TARGET_HAS_div2_i64 0
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 1
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#define TCG_TARGET_HAS_ext16u_i64 1
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_andc_i64 0
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#define TCG_TARGET_HAS_eqv_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_orc_i64 0
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_movcond_i64 0
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#endif /* TCG_TARGET_REG_BITS == 64 */
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/* Number of registers available.
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For 32 bit hosts, we need more than 8 registers (call arguments). */
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/* #define TCG_TARGET_NB_REGS 8 */
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#define TCG_TARGET_NB_REGS 16
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/* #define TCG_TARGET_NB_REGS 32 */
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/* List of registers which are used by TCG. */
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typedef enum {
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TCG_REG_R0 = 0,
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TCG_REG_R1,
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TCG_REG_R2,
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TCG_REG_R3,
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TCG_REG_R4,
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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TCG_AREG0 = TCG_REG_R7,
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#if TCG_TARGET_NB_REGS >= 16
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_R15,
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#if TCG_TARGET_NB_REGS >= 32
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TCG_REG_R16,
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TCG_REG_R17,
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TCG_REG_R18,
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TCG_REG_R19,
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TCG_REG_R20,
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TCG_REG_R21,
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TCG_REG_R22,
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TCG_REG_R23,
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TCG_REG_R24,
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TCG_REG_R25,
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TCG_REG_R26,
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TCG_REG_R27,
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TCG_REG_R28,
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TCG_REG_R29,
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TCG_REG_R30,
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TCG_REG_R31,
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#endif
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#endif
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/* Special value UINT8_MAX is used by TCI to encode constant values. */
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TCG_CONST = UINT8_MAX
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} TCGReg;
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void tci_disas(uint8_t opc);
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tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
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#define tcg_qemu_tb_exec tcg_qemu_tb_exec
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static inline void flush_icache_range(tcg_target_ulong start,
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tcg_target_ulong stop)
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{
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}
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#endif /* TCG_TARGET_H */
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