mirror of https://gitlab.com/qemu-project/qemu
e1be0a576b
For v8M, the NVIC has a new set of registers per interrupt, NVIC_ITNS<n>. These determine whether the interrupt targets Secure or Non-secure state. Implement the register read/write code for these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER, NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure accesses to fields corresponding to interrupts which are configured to target secure state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org |
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| .. | ||
| Makefile.objs | ||
| allwinner-a10-pic.c | ||
| apic.c | ||
| apic_common.c | ||
| arm_gic.c | ||
| arm_gic_common.c | ||
| arm_gic_kvm.c | ||
| arm_gicv2m.c | ||
| arm_gicv3.c | ||
| arm_gicv3_common.c | ||
| arm_gicv3_cpuif.c | ||
| arm_gicv3_dist.c | ||
| arm_gicv3_its_common.c | ||
| arm_gicv3_its_kvm.c | ||
| arm_gicv3_kvm.c | ||
| arm_gicv3_redist.c | ||
| armv7m_nvic.c | ||
| aspeed_vic.c | ||
| bcm2835_ic.c | ||
| bcm2836_control.c | ||
| etraxfs_pic.c | ||
| exynos4210_combiner.c | ||
| exynos4210_gic.c | ||
| gic_internal.h | ||
| gicv3_internal.h | ||
| grlib_irqmp.c | ||
| heathrow_pic.c | ||
| i8259.c | ||
| i8259_common.c | ||
| imx_avic.c | ||
| intc.c | ||
| ioapic.c | ||
| ioapic_common.c | ||
| lm32_pic.c | ||
| mips_gic.c | ||
| nios2_iic.c | ||
| omap_intc.c | ||
| openpic.c | ||
| openpic_kvm.c | ||
| pl190.c | ||
| puv3_intc.c | ||
| realview_gic.c | ||
| s390_flic.c | ||
| s390_flic_kvm.c | ||
| sh_intc.c | ||
| slavio_intctl.c | ||
| trace-events | ||
| vgic_common.h | ||
| xics.c | ||
| xics_kvm.c | ||
| xics_pnv.c | ||
| xics_spapr.c | ||
| xilinx_intc.c | ||