qemu/target
Peter Maydell e0e875a68a target/i386: Use assert() to sanity-check b1 in SSE decode
In the SSE decode function gen_sse(), we combine a byte
'b' and a value 'b1' which can be [0..3], and switch on them:
   b |= (b1 << 8);
   switch (b) {
   ...
   default:
   unknown_op:
       gen_unknown_opcode(env, s);
       return;
   }

In three cases inside this switch, we were then also checking for
 "if (b1 >= 2) { goto unknown_op; }".
However, this can never happen, because the 'case' values in each place
are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3)
cases to the default already.

This check was added in commit c045af25a5 in 2010; the added code
was unnecessary then as well, and was apparently intended only to
ensure that we never accidentally ended up indexing off the end
of an sse_op_table with only 2 entries as a result of future bugs
in the decode logic.

Change the checks to assert() instead, and make sure they're always
immediately before the array access they are protecting.

Fixes: Coverity CID 1460207
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-15 10:35:26 +00:00
..
alpha target/alpha: Implement alpha_cpu_record_sigbus 2021-11-02 07:00:52 -04:00
arm target/arm: Suppress bp for exceptions with more priority 2021-12-15 10:35:26 +00:00
avr target/avr: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
cris target/cris: Make cris_cpu_tlb_fill sysemu only 2021-11-02 07:00:52 -04:00
hexagon This series adds support for the Hexagon Vector eXtensions (HVX) 2021-11-04 06:34:36 -04:00
hppa target/hppa: Make hppa_cpu_tlb_fill sysemu only 2021-11-02 07:00:52 -04:00
i386 target/i386: Use assert() to sanity-check b1 in SSE decode 2021-12-15 10:35:26 +00:00
m68k target/m68k: Make m68k_cpu_tlb_fill sysemu only 2021-11-02 07:00:52 -04:00
microblaze target/microblaze: Do not set MO_ALIGN for user-only 2021-11-02 07:00:52 -04:00
mips MIPS patches queue 2021-11-02 15:12:11 -04:00
nios2 target/nios2: Implement nios2_cpu_record_sigsegv 2021-11-02 07:00:52 -04:00
openrisc target/openrisc: Make openrisc_cpu_tlb_fill sysemu only 2021-11-02 07:00:52 -04:00
ppc target/ppc: fix Hash64 MMU update of PTE bit R 2021-11-29 21:00:08 +01:00
riscv target/riscv: machine: Sort the .subsections 2021-11-17 19:18:22 +10:00
rx target/rx: Drop checks for singlestep_enabled 2021-10-15 16:39:14 -07:00
s390x target/s390x/cpu.h: Remove unused SIGP_MODE defines 2021-11-17 10:17:28 +01:00
sh4 target/sh4: Set fault address in superh_cpu_do_unaligned_access 2021-11-02 07:00:52 -04:00
sparc target/sparc: Set fault address in sparc_cpu_do_unaligned_access 2021-11-02 07:00:52 -04:00
tricore target/tricore: Drop check for singlestep_enabled 2021-10-15 16:39:14 -07:00
xtensa Trivial patches branch pull request 20211101 v2 2021-11-03 11:24:09 -04:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00