022c7550d9
Reduce reliance on absolute values(by passing pc difference) to prepare for PC-relative translation. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230526072124.298466-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
52 lines
1.7 KiB
C++
52 lines
1.7 KiB
C++
/*
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* RISC-V translation routines for the RISC-V Zawrs Extension.
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*
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* Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.io
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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static bool trans_wrs(DisasContext *ctx)
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{
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if (!ctx->cfg_ptr->ext_zawrs) {
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return false;
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}
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/*
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* The specification says:
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* While stalled, an implementation is permitted to occasionally
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* terminate the stall and complete execution for any reason.
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*
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* So let's just exit TB and return to the main loop.
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*/
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/* Clear the load reservation (if any). */
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tcg_gen_movi_tl(load_res, -1);
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gen_update_pc(ctx, ctx->cur_insn_len);
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tcg_gen_exit_tb(NULL, 0);
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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#define GEN_TRANS_WRS(insn) \
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static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \
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{ \
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(void)a; \
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return trans_wrs(ctx); \
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}
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GEN_TRANS_WRS(wrs_nto)
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GEN_TRANS_WRS(wrs_sto)
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