e0d6e6a5e7
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1411718914-6608-10-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
519 lines
15 KiB
C
519 lines
15 KiB
C
/*
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* AArch64 specific helpers
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*
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* Copyright (c) 2013 Alexander Graf <agraf@suse.de>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "exec/helper-proto.h"
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#include "qemu/host-utils.h"
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#include "sysemu/sysemu.h"
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#include "qemu/bitops.h"
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#include "internals.h"
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#include "qemu/crc32c.h"
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#include <zlib.h> /* For crc32 */
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/* C2.4.7 Multiply and divide */
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/* special cases for 0 and LLONG_MIN are mandated by the standard */
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uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
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{
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if (den == 0) {
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return 0;
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}
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return num / den;
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}
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int64_t HELPER(sdiv64)(int64_t num, int64_t den)
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{
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if (den == 0) {
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return 0;
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}
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if (num == LLONG_MIN && den == -1) {
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return LLONG_MIN;
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}
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return num / den;
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}
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uint64_t HELPER(clz64)(uint64_t x)
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{
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return clz64(x);
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}
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uint64_t HELPER(cls64)(uint64_t x)
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{
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return clrsb64(x);
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}
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uint32_t HELPER(cls32)(uint32_t x)
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{
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return clrsb32(x);
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}
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uint32_t HELPER(clz32)(uint32_t x)
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{
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return clz32(x);
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}
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uint64_t HELPER(rbit64)(uint64_t x)
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{
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/* assign the correct byte position */
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x = bswap64(x);
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/* assign the correct nibble position */
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x = ((x & 0xf0f0f0f0f0f0f0f0ULL) >> 4)
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| ((x & 0x0f0f0f0f0f0f0f0fULL) << 4);
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/* assign the correct bit position */
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x = ((x & 0x8888888888888888ULL) >> 3)
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| ((x & 0x4444444444444444ULL) >> 1)
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| ((x & 0x2222222222222222ULL) << 1)
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| ((x & 0x1111111111111111ULL) << 3);
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return x;
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}
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/* Convert a softfloat float_relation_ (as returned by
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* the float*_compare functions) to the correct ARM
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* NZCV flag state.
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*/
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static inline uint32_t float_rel_to_flags(int res)
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{
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uint64_t flags;
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switch (res) {
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case float_relation_equal:
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flags = PSTATE_Z | PSTATE_C;
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break;
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case float_relation_less:
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flags = PSTATE_N;
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break;
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case float_relation_greater:
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flags = PSTATE_C;
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break;
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case float_relation_unordered:
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default:
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flags = PSTATE_C | PSTATE_V;
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break;
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}
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return flags;
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}
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uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
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{
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return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
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}
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uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
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{
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return float_rel_to_flags(float32_compare(x, y, fp_status));
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}
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uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
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{
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return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
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}
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uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
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{
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return float_rel_to_flags(float64_compare(x, y, fp_status));
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}
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float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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if ((float32_is_zero(a) && float32_is_infinity(b)) ||
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(float32_is_infinity(a) && float32_is_zero(b))) {
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/* 2.0 with the sign bit set to sign(A) XOR sign(B) */
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return make_float32((1U << 30) |
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((float32_val(a) ^ float32_val(b)) & (1U << 31)));
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}
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return float32_mul(a, b, fpst);
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}
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float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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if ((float64_is_zero(a) && float64_is_infinity(b)) ||
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(float64_is_infinity(a) && float64_is_zero(b))) {
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/* 2.0 with the sign bit set to sign(A) XOR sign(B) */
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return make_float64((1ULL << 62) |
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((float64_val(a) ^ float64_val(b)) & (1ULL << 63)));
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}
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return float64_mul(a, b, fpst);
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}
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uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
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uint32_t rn, uint32_t numregs)
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{
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/* Helper function for SIMD TBL and TBX. We have to do the table
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* lookup part for the 64 bits worth of indices we're passed in.
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* result is the initial results vector (either zeroes for TBL
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* or some guest values for TBX), rn the register number where
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* the table starts, and numregs the number of registers in the table.
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* We return the results of the lookups.
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*/
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int shift;
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for (shift = 0; shift < 64; shift += 8) {
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int index = extract64(indices, shift, 8);
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if (index < 16 * numregs) {
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/* Convert index (a byte offset into the virtual table
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* which is a series of 128-bit vectors concatenated)
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* into the correct vfp.regs[] element plus a bit offset
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* into that element, bearing in mind that the table
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* can wrap around from V31 to V0.
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*/
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int elt = (rn * 2 + (index >> 3)) % 64;
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int bitidx = (index & 7) * 8;
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uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8);
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result = deposit64(result, shift, 8, val);
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}
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}
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return result;
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}
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/* 64bit/double versions of the neon float compare functions */
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uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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return -float64_eq_quiet(a, b, fpst);
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}
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uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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return -float64_le(b, a, fpst);
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}
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uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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return -float64_lt(b, a, fpst);
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}
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/* Reciprocal step and sqrt step. Note that unlike the A32/T32
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* versions, these do a fully fused multiply-add or
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* multiply-add-and-halve.
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*/
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#define float32_two make_float32(0x40000000)
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#define float32_three make_float32(0x40400000)
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#define float32_one_point_five make_float32(0x3fc00000)
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#define float64_two make_float64(0x4000000000000000ULL)
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#define float64_three make_float64(0x4008000000000000ULL)
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#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
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float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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a = float32_chs(a);
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if ((float32_is_infinity(a) && float32_is_zero(b)) ||
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(float32_is_infinity(b) && float32_is_zero(a))) {
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return float32_two;
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}
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return float32_muladd(a, b, float32_two, 0, fpst);
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}
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float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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a = float64_chs(a);
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if ((float64_is_infinity(a) && float64_is_zero(b)) ||
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(float64_is_infinity(b) && float64_is_zero(a))) {
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return float64_two;
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}
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return float64_muladd(a, b, float64_two, 0, fpst);
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}
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float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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a = float32_chs(a);
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if ((float32_is_infinity(a) && float32_is_zero(b)) ||
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(float32_is_infinity(b) && float32_is_zero(a))) {
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return float32_one_point_five;
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}
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return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
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}
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float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
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{
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float_status *fpst = fpstp;
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a = float64_chs(a);
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if ((float64_is_infinity(a) && float64_is_zero(b)) ||
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(float64_is_infinity(b) && float64_is_zero(a))) {
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return float64_one_point_five;
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}
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return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
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}
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/* Pairwise long add: add pairs of adjacent elements into
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* double-width elements in the result (eg _s8 is an 8x8->16 op)
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*/
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uint64_t HELPER(neon_addlp_s8)(uint64_t a)
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{
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uint64_t nsignmask = 0x0080008000800080ULL;
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uint64_t wsignmask = 0x8000800080008000ULL;
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uint64_t elementmask = 0x00ff00ff00ff00ffULL;
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uint64_t tmp1, tmp2;
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uint64_t res, signres;
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/* Extract odd elements, sign extend each to a 16 bit field */
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tmp1 = a & elementmask;
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tmp1 ^= nsignmask;
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tmp1 |= wsignmask;
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tmp1 = (tmp1 - nsignmask) ^ wsignmask;
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/* Ditto for the even elements */
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tmp2 = (a >> 8) & elementmask;
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tmp2 ^= nsignmask;
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tmp2 |= wsignmask;
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tmp2 = (tmp2 - nsignmask) ^ wsignmask;
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/* calculate the result by summing bits 0..14, 16..22, etc,
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* and then adjusting the sign bits 15, 23, etc manually.
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* This ensures the addition can't overflow the 16 bit field.
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*/
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signres = (tmp1 ^ tmp2) & wsignmask;
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res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
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res ^= signres;
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return res;
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}
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uint64_t HELPER(neon_addlp_u8)(uint64_t a)
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{
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uint64_t tmp;
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tmp = a & 0x00ff00ff00ff00ffULL;
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tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
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return tmp;
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}
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uint64_t HELPER(neon_addlp_s16)(uint64_t a)
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{
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int32_t reslo, reshi;
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reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
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reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
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return (uint32_t)reslo | (((uint64_t)reshi) << 32);
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}
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uint64_t HELPER(neon_addlp_u16)(uint64_t a)
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{
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uint64_t tmp;
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tmp = a & 0x0000ffff0000ffffULL;
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tmp += (a >> 16) & 0x0000ffff0000ffffULL;
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return tmp;
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}
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/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
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float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
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{
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float_status *fpst = fpstp;
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uint32_t val32, sbit;
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int32_t exp;
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if (float32_is_any_nan(a)) {
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float32 nan = a;
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if (float32_is_signaling_nan(a)) {
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float_raise(float_flag_invalid, fpst);
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nan = float32_maybe_silence_nan(a);
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}
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if (fpst->default_nan_mode) {
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nan = float32_default_nan;
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}
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return nan;
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}
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val32 = float32_val(a);
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sbit = 0x80000000ULL & val32;
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exp = extract32(val32, 23, 8);
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if (exp == 0) {
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return make_float32(sbit | (0xfe << 23));
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} else {
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return make_float32(sbit | (~exp & 0xff) << 23);
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}
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}
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float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
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{
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float_status *fpst = fpstp;
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uint64_t val64, sbit;
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int64_t exp;
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if (float64_is_any_nan(a)) {
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float64 nan = a;
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if (float64_is_signaling_nan(a)) {
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float_raise(float_flag_invalid, fpst);
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nan = float64_maybe_silence_nan(a);
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}
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if (fpst->default_nan_mode) {
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nan = float64_default_nan;
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}
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return nan;
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}
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val64 = float64_val(a);
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sbit = 0x8000000000000000ULL & val64;
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exp = extract64(float64_val(a), 52, 11);
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if (exp == 0) {
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return make_float64(sbit | (0x7feULL << 52));
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} else {
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return make_float64(sbit | (~exp & 0x7ffULL) << 52);
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}
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}
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float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
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{
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/* Von Neumann rounding is implemented by using round-to-zero
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* and then setting the LSB of the result if Inexact was raised.
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*/
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float32 r;
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float_status *fpst = &env->vfp.fp_status;
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float_status tstat = *fpst;
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int exflags;
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set_float_rounding_mode(float_round_to_zero, &tstat);
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set_float_exception_flags(0, &tstat);
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r = float64_to_float32(a, &tstat);
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r = float32_maybe_silence_nan(r);
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exflags = get_float_exception_flags(&tstat);
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if (exflags & float_flag_inexact) {
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r = make_float32(float32_val(r) | 1);
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}
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exflags |= get_float_exception_flags(fpst);
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set_float_exception_flags(exflags, fpst);
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return r;
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}
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/* 64-bit versions of the CRC helpers. Note that although the operation
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* (and the prototypes of crc32c() and crc32() mean that only the bottom
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* 32 bits of the accumulator and result are used, we pass and return
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* uint64_t for convenience of the generated code. Unlike the 32-bit
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* instruction set versions, val may genuinely have 64 bits of data in it.
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* The upper bytes of val (above the number specified by 'bytes') must have
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* been zeroed out by the caller.
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*/
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uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes)
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{
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uint8_t buf[8];
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stq_le_p(buf, val);
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/* zlib crc32 converts the accumulator and output to one's complement. */
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return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
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}
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uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
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{
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uint8_t buf[8];
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stq_le_p(buf, val);
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/* Linux crc32c converts the output to one's complement. */
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return crc32c(acc, buf, bytes) ^ 0xffffffff;
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}
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/* Handle a CPU exception. */
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void aarch64_cpu_do_interrupt(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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unsigned int new_el = arm_excp_target_el(cs, cs->exception_index);
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target_ulong addr = env->cp15.vbar_el[new_el];
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unsigned int new_mode = aarch64_pstate_mode(new_el, true);
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int i;
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if (arm_current_pl(env) < new_el) {
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if (env->aarch64) {
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addr += 0x400;
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} else {
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addr += 0x600;
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}
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} else if (pstate_read(env) & PSTATE_SP) {
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addr += 0x200;
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}
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arm_log_exception(cs->exception_index);
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qemu_log_mask(CPU_LOG_INT, "...from EL%d\n", arm_current_pl(env));
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if (qemu_loglevel_mask(CPU_LOG_INT)
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&& !excp_is_internal(cs->exception_index)) {
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qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%" PRIx32 "\n",
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env->exception.syndrome);
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}
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switch (cs->exception_index) {
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case EXCP_PREFETCH_ABORT:
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case EXCP_DATA_ABORT:
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env->cp15.far_el[new_el] = env->exception.vaddress;
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qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
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env->cp15.far_el[new_el]);
|
|
/* fall through */
|
|
case EXCP_BKPT:
|
|
case EXCP_UDEF:
|
|
case EXCP_SWI:
|
|
case EXCP_HVC:
|
|
case EXCP_HYP_TRAP:
|
|
case EXCP_SMC:
|
|
env->cp15.esr_el[new_el] = env->exception.syndrome;
|
|
break;
|
|
case EXCP_IRQ:
|
|
addr += 0x80;
|
|
break;
|
|
case EXCP_FIQ:
|
|
addr += 0x100;
|
|
break;
|
|
default:
|
|
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
|
|
}
|
|
|
|
if (is_a64(env)) {
|
|
env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
|
|
aarch64_save_sp(env, arm_current_pl(env));
|
|
env->elr_el[new_el] = env->pc;
|
|
} else {
|
|
env->banked_spsr[0] = cpsr_read(env);
|
|
if (!env->thumb) {
|
|
env->cp15.esr_el[new_el] |= 1 << 25;
|
|
}
|
|
env->elr_el[new_el] = env->regs[15];
|
|
|
|
for (i = 0; i < 15; i++) {
|
|
env->xregs[i] = env->regs[i];
|
|
}
|
|
|
|
env->condexec_bits = 0;
|
|
}
|
|
|
|
pstate_write(env, PSTATE_DAIF | new_mode);
|
|
env->aarch64 = 1;
|
|
aarch64_restore_sp(env, new_el);
|
|
|
|
env->pc = addr;
|
|
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
|
|
}
|