Daniel Henrique Barboza e442635317 target/riscv/kvm: remove sneaky strerrorname_np() instance ... Commit d424db2354 excluded some strerrorname_np() instances because they break musl libc builds. Another instance happened to slip by via commit d4ff3da8f4. Remove it before it causes trouble again. Fixes: d4ff3da8f4 (target/riscv/kvm: initialize 'vlenb' via get-reg-list) Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>		2024-04-29 15:26:56 +03:00
..
insn_trans	target/riscv: enable 'vstart_eq_zero' in the end of insns	2024-03-22 15:24:37 +10:00
kvm	target/riscv/kvm: remove sneaky strerrorname_np() instance	2024-04-29 15:26:56 +03:00
tcg	target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin	2024-03-22 15:31:09 +10:00
Kconfig	kconfig: use "select" to enable semihosting	2024-02-09 17:52:30 +00:00
XVentanaCondOps.decode	…
arch_dump.c	…
bitmanip_helper.c	…
common-semi-target.h	…
cpu-param.h	target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'	2024-04-26 15:31:37 +02:00
cpu-qom.h	target/riscv: add rv32i, rv32e and rv64e CPUs	2024-02-09 20:49:41 +10:00
cpu.c	hw, target: Add ResetType argument to hold and exit phase methods	2024-04-25 10:21:06 +01:00
cpu.h	target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'	2024-04-26 15:31:37 +02:00
cpu_bits.h	target/riscv: FCSR doesn't contain vxrm and vxsat	2024-02-09 20:43:14 +10:00
cpu_cfg.h	target/riscv: do not enable all named features by default	2024-03-22 15:10:45 +10:00
cpu_helper.c	target/riscv: Fix mode in riscv_tlb_fill	2024-03-22 15:32:33 +10:00
cpu_user.h	…
cpu_vendorid.h	…
crypto_helper.c	…
csr.c	target/riscv: UPDATE xATP write CSR	2024-03-08 16:38:09 +10:00
debug.c	target/riscv: Implement optional CSR mcontext of debug Sdtrig extension	2024-02-09 20:40:32 +10:00
debug.h	exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header	2024-04-26 17:03:05 +02:00
fpu_helper.c	…
gdbstub.c	gdbstub: Add members to identify registers to GDBFeature	2024-02-28 09:10:11 +00:00
helper.h	…
insn16.decode	…
insn32.decode	…
instmap.h	…
internals.h	…
m128_helper.c	…
machine.c	target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit	2024-03-08 20:48:03 +10:00
meson.build	…
monitor.c	…
op_helper.c	…
pmp.c	…
pmp.h	…
pmu.c	…
pmu.h	target/riscv: Add missing include guard in pmu.h	2024-03-08 16:39:32 +10:00
riscv-qmp-cmds.c	target: Improve error reporting for CpuModelInfo member @props	2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h	…
time_helper.c	…
time_helper.h	…
trace-events	…
trace.h	…
translate.c	target/riscv: Use insn_start from DisasContextBase	2024-04-09 07:45:09 -10:00
vcrypto_helper.c	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
vector_helper.c	target/riscv/vector_helper.c: optimize loops in ldst helpers	2024-03-22 15:28:19 +10:00
vector_internals.c	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
vector_internals.h	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
xthead.decode	…
zce_helper.c	…