e07fb4b50b
Claim ACS support in the generic PCIe root port to allow passthrough of individual functions of a device to different guests (in a nested virt.setting) with VFIO. Without this patch, all functions of a device, such as all VFs of an SR/IOV device, will end up in the same IOMMU group. A similar situation occurs on Windows with Hyper-V. In the single function device case, it also has a small cosmetic benefit in that the root port itself is not grouped with the device. VFIO handles that situation in that binding rules only apply to endpoints, so it does not limit passthrough in those cases. Signed-off-by: Knut Omang <knut.omang@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <319460b483f566dd57487eb3dd340ed4c10aa53c.1550768238.git-series.knut.omang@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
86 lines
2.5 KiB
C
86 lines
2.5 KiB
C
/*
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* pcie_port.h
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef QEMU_PCIE_PORT_H
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#define QEMU_PCIE_PORT_H
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#define TYPE_PCIE_PORT "pcie-port"
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#define PCIE_PORT(obj) OBJECT_CHECK(PCIEPort, (obj), TYPE_PCIE_PORT)
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struct PCIEPort {
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/*< private >*/
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PCIBridge parent_obj;
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/*< public >*/
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/* pci express switch port */
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uint8_t port;
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};
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void pcie_port_init_reg(PCIDevice *d);
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#define TYPE_PCIE_SLOT "pcie-slot"
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#define PCIE_SLOT(obj) OBJECT_CHECK(PCIESlot, (obj), TYPE_PCIE_SLOT)
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struct PCIESlot {
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/*< private >*/
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PCIEPort parent_obj;
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/*< public >*/
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/* pci express switch port with slot */
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uint8_t chassis;
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uint16_t slot;
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PCIExpLinkSpeed speed;
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PCIExpLinkWidth width;
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QLIST_ENTRY(PCIESlot) next;
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};
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void pcie_chassis_create(uint8_t chassis_number);
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PCIESlot *pcie_chassis_find_slot(uint8_t chassis, uint16_t slot);
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int pcie_chassis_add_slot(struct PCIESlot *slot);
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void pcie_chassis_del_slot(PCIESlot *s);
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#define TYPE_PCIE_ROOT_PORT "pcie-root-port-base"
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#define PCIE_ROOT_PORT_CLASS(klass) \
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OBJECT_CLASS_CHECK(PCIERootPortClass, (klass), TYPE_PCIE_ROOT_PORT)
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#define PCIE_ROOT_PORT_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PCIERootPortClass, (obj), TYPE_PCIE_ROOT_PORT)
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typedef struct PCIERootPortClass {
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PCIDeviceClass parent_class;
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DeviceRealize parent_realize;
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uint8_t (*aer_vector)(const PCIDevice *dev);
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int (*interrupts_init)(PCIDevice *dev, Error **errp);
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void (*interrupts_uninit)(PCIDevice *dev);
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int exp_offset;
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int aer_offset;
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int ssvid_offset;
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int acs_offset; /* If nonzero, optional ACS capability offset */
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int ssid;
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} PCIERootPortClass;
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#endif /* QEMU_PCIE_PORT_H */
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