e967413fe0
Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP and CXL Type 3 end points. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230913132523.29780-5-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
482 lines
18 KiB
C
482 lines
18 KiB
C
/*
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* CXL Utility library for components
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*
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* Copyright(C) 2020 Intel Corporation.
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "hw/pci/pci.h"
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#include "hw/cxl/cxl.h"
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/* CXL r3.0 Section 8.2.4.19.1 CXL HDM Decoder Capability Register */
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int cxl_decoder_count_enc(int count)
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{
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switch (count) {
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case 1: return 0x0;
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case 2: return 0x1;
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case 4: return 0x2;
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case 6: return 0x3;
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case 8: return 0x4;
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case 10: return 0x5;
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/* Switches and Host Bridges may have more than 10 decoders */
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case 12: return 0x6;
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case 14: return 0x7;
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case 16: return 0x8;
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case 20: return 0x9;
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case 24: return 0xa;
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case 28: return 0xb;
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case 32: return 0xc;
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}
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return 0;
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}
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int cxl_decoder_count_dec(int enc_cnt)
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{
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switch (enc_cnt) {
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case 0x0: return 1;
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case 0x1: return 2;
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case 0x2: return 4;
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case 0x3: return 6;
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case 0x4: return 8;
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case 0x5: return 10;
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/* Switches and Host Bridges may have more than 10 decoders */
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case 0x6: return 12;
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case 0x7: return 14;
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case 0x8: return 16;
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case 0x9: return 20;
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case 0xa: return 24;
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case 0xb: return 28;
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case 0xc: return 32;
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}
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return 0;
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}
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hwaddr cxl_decode_ig(int ig)
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{
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return 1ULL << (ig + 8);
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}
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static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset,
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unsigned size)
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{
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CXLComponentState *cxl_cstate = opaque;
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ComponentRegisters *cregs = &cxl_cstate->crb;
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if (size == 8) {
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qemu_log_mask(LOG_UNIMP,
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"CXL 8 byte cache mem registers not implemented\n");
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return 0;
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}
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if (cregs->special_ops && cregs->special_ops->read) {
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return cregs->special_ops->read(cxl_cstate, offset, size);
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} else {
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return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
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}
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}
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static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset,
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uint32_t value)
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{
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ComponentRegisters *cregs = &cxl_cstate->crb;
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uint32_t *cache_mem = cregs->cache_mem_registers;
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bool should_commit = false;
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bool should_uncommit = false;
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switch (offset) {
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case A_CXL_HDM_DECODER0_CTRL:
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case A_CXL_HDM_DECODER1_CTRL:
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case A_CXL_HDM_DECODER2_CTRL:
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case A_CXL_HDM_DECODER3_CTRL:
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should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
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should_uncommit = !should_commit;
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break;
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default:
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break;
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}
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if (should_commit) {
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value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0);
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value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
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} else if (should_uncommit) {
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value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0);
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value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0);
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}
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stl_le_p((uint8_t *)cache_mem + offset, value);
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}
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static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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CXLComponentState *cxl_cstate = opaque;
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ComponentRegisters *cregs = &cxl_cstate->crb;
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uint32_t mask;
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if (size == 8) {
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qemu_log_mask(LOG_UNIMP,
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"CXL 8 byte cache mem registers not implemented\n");
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return;
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}
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mask = cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cache_mem_regs_write_mask)];
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value &= mask;
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/* RO bits should remain constant. Done by reading existing value */
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value |= ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)];
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if (cregs->special_ops && cregs->special_ops->write) {
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cregs->special_ops->write(cxl_cstate, offset, value, size);
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return;
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}
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if (offset >= A_CXL_HDM_DECODER_CAPABILITY &&
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offset <= A_CXL_HDM_DECODER3_TARGET_LIST_HI) {
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dumb_hdm_handler(cxl_cstate, offset, value);
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} else {
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cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_registers)] = value;
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}
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}
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/*
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* 8.2.3
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* The access restrictions specified in Section 8.2.2 also apply to CXL 2.0
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* Component Registers.
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*
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* 8.2.2
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* • A 32 bit register shall be accessed as a 4 Bytes quantity. Partial
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* reads are not permitted.
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* • A 64 bit register shall be accessed as a 8 Bytes quantity. Partial
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* reads are not permitted.
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*
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* As of the spec defined today, only 4 byte registers exist.
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*/
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static const MemoryRegionOps cache_mem_ops = {
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.read = cxl_cache_mem_read_reg,
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.write = cxl_cache_mem_write_reg,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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.unaligned = false,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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};
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void cxl_component_register_block_init(Object *obj,
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CXLComponentState *cxl_cstate,
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const char *type)
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{
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ComponentRegisters *cregs = &cxl_cstate->crb;
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memory_region_init(&cregs->component_registers, obj, type,
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CXL2_COMPONENT_BLOCK_SIZE);
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/* io registers controls link which we don't care about in QEMU */
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memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io",
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CXL2_COMPONENT_IO_REGION_SIZE);
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memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs,
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".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE);
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memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io);
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memory_region_add_subregion(&cregs->component_registers,
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CXL2_COMPONENT_IO_REGION_SIZE,
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&cregs->cache_mem);
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}
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static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)
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{
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/*
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* Error status is RW1C but given bits are not yet set, it can
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* be handled as RO.
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*/
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stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0);
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stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff);
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/* Bits 12-13 and 17-31 reserved in CXL 2.0 */
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stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
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stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
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stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
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stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
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stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0);
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stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f);
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stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f);
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stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f);
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/* CXL switches and devices must set */
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stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200);
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}
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static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
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enum reg_type type)
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{
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int decoder_count = CXL_HDM_DECODER_COUNT;
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int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO;
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int i;
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT,
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cxl_decoder_count_enc(decoder_count));
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 0);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL,
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HDM_DECODER_ENABLE, 0);
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write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3;
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for (i = 0; i < decoder_count; i++) {
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write_msk[R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc] = 0xf0000000;
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write_msk[R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc] = 0xffffffff;
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write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc] = 0xf0000000;
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write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc] = 0xffffffff;
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write_msk[R_CXL_HDM_DECODER0_CTRL + i * hdm_inc] = 0x13ff;
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if (type == CXL2_DEVICE ||
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type == CXL2_TYPE3_DEVICE ||
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type == CXL2_LOGICAL_DEVICE) {
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write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * hdm_inc] =
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0xf0000000;
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} else {
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write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * hdm_inc] =
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0xffffffff;
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}
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write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * hdm_inc] = 0xffffffff;
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}
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}
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void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk,
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enum reg_type type)
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{
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int caps = 0;
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/*
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* In CXL 2.0 the capabilities required for each CXL component are such that,
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* with the ordering chosen here, a single number can be used to define
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* which capabilities should be provided.
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*/
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switch (type) {
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case CXL2_DOWNSTREAM_PORT:
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case CXL2_DEVICE:
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/* RAS, Link */
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caps = 2;
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break;
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case CXL2_UPSTREAM_PORT:
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case CXL2_TYPE3_DEVICE:
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case CXL2_LOGICAL_DEVICE:
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/* + HDM */
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caps = 3;
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break;
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case CXL2_ROOT_PORT:
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/* + Extended Security, + Snoop */
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caps = 5;
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break;
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default:
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abort();
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}
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memset(reg_state, 0, CXL2_COMPONENT_CM_REGION_SIZE);
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/* CXL Capability Header Register */
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ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ID, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, VERSION, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 1);
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ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps);
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#define init_cap_reg(reg, id, version) \
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QEMU_BUILD_BUG_ON(CXL_##reg##_REGISTERS_OFFSET == 0); \
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do { \
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int which = R_CXL_##reg##_CAPABILITY_HEADER; \
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reg_state[which] = FIELD_DP32(reg_state[which], \
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CXL_##reg##_CAPABILITY_HEADER, ID, id); \
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reg_state[which] = \
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FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, \
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VERSION, version); \
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reg_state[which] = \
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FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PTR, \
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CXL_##reg##_REGISTERS_OFFSET); \
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} while (0)
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init_cap_reg(RAS, 2, 2);
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ras_init_common(reg_state, write_msk);
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init_cap_reg(LINK, 4, 2);
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if (caps < 3) {
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return;
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}
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init_cap_reg(HDM, 5, 1);
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hdm_init_common(reg_state, write_msk, type);
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if (caps < 5) {
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return;
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}
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init_cap_reg(EXTSEC, 6, 1);
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init_cap_reg(SNOOP, 8, 1);
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#undef init_cap_reg
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}
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/*
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* Helper to creates a DVSEC header for a CXL entity. The caller is responsible
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* for tracking the valid offset.
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*
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* This function will build the DVSEC header on behalf of the caller and then
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* copy in the remaining data for the vendor specific bits.
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* It will also set up appropriate write masks.
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*/
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void cxl_component_create_dvsec(CXLComponentState *cxl,
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enum reg_type cxl_dev_type, uint16_t length,
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uint16_t type, uint8_t rev, uint8_t *body)
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{
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PCIDevice *pdev = cxl->pdev;
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uint16_t offset = cxl->dvsec_offset;
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uint8_t *wmask = pdev->wmask;
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assert(offset >= PCI_CFG_SPACE_SIZE &&
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((offset + length) < PCI_CFG_SPACE_EXP_SIZE));
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assert((length & 0xf000) == 0);
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assert((rev & ~0xf) == 0);
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/* Create the DVSEC in the MCFG space */
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pcie_add_capability(pdev, PCI_EXT_CAP_ID_DVSEC, 1, offset, length);
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pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET,
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(length << 20) | (rev << 16) | CXL_VENDOR_ID);
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pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type);
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memcpy(pdev->config + offset + sizeof(DVSECHeader),
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body + sizeof(DVSECHeader),
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length - sizeof(DVSECHeader));
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/* Configure write masks */
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switch (type) {
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case PCIE_CXL_DEVICE_DVSEC:
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/* Cntrl RW Lock - so needs explicit blocking when lock is set */
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wmask[offset + offsetof(CXLDVSECDevice, ctrl)] = 0xFD;
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wmask[offset + offsetof(CXLDVSECDevice, ctrl) + 1] = 0x4F;
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/* Status is RW1CS */
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wmask[offset + offsetof(CXLDVSECDevice, ctrl2)] = 0x0F;
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/* Lock is RW Once */
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wmask[offset + offsetof(CXLDVSECDevice, lock)] = 0x01;
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/* range1/2_base_high/low is RW Lock */
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wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi)] = 0xFF;
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wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 1] = 0xFF;
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wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 2] = 0xFF;
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wmask[offset + offsetof(CXLDVSECDevice, range1_base_hi) + 3] = 0xFF;
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wmask[offset + offsetof(CXLDVSECDevice, range1_base_lo) + 3] = 0xF0;
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wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi)] = 0xFF;
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wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 1] = 0xFF;
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wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 2] = 0xFF;
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wmask[offset + offsetof(CXLDVSECDevice, range2_base_hi) + 3] = 0xFF;
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wmask[offset + offsetof(CXLDVSECDevice, range2_base_lo) + 3] = 0xF0;
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break;
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case NON_CXL_FUNCTION_MAP_DVSEC:
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break; /* Not yet implemented */
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case EXTENSIONS_PORT_DVSEC:
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wmask[offset + offsetof(CXLDVSECPortExtensions, control)] = 0x0F;
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wmask[offset + offsetof(CXLDVSECPortExtensions, control) + 1] = 0x40;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_base)] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_limit)] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base)] = 0xF0;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base) + 1] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit)] = 0xF0;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit) + 1] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base)] = 0xF0;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base) + 1] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit)] = 0xF0;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit) + 1] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high)] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 1] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 2] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 3] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high)] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 1] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 2] = 0xFF;
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wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 3] = 0xFF;
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break;
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case GPF_PORT_DVSEC:
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wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F;
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wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl) + 1] = 0x0F;
|
|
wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl)] = 0x0F;
|
|
wmask[offset + offsetof(CXLDVSECPortGPF, phase2_ctrl) + 1] = 0x0F;
|
|
break;
|
|
case GPF_DEVICE_DVSEC:
|
|
wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration)] = 0x0F;
|
|
wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_duration) + 1] = 0x0F;
|
|
wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power)] = 0xFF;
|
|
wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 1] = 0xFF;
|
|
wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 2] = 0xFF;
|
|
wmask[offset + offsetof(CXLDVSECDeviceGPF, phase2_power) + 3] = 0xFF;
|
|
break;
|
|
case PCIE_FLEXBUS_PORT_DVSEC:
|
|
switch (cxl_dev_type) {
|
|
case CXL2_ROOT_PORT:
|
|
/* No MLD */
|
|
wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xbd;
|
|
break;
|
|
case CXL2_DOWNSTREAM_PORT:
|
|
wmask[offset + offsetof(CXLDVSECPortFlexBus, ctrl)] = 0xfd;
|
|
break;
|
|
default: /* Registers are RO for other component types */
|
|
break;
|
|
}
|
|
/* There are rw1cs bits in the status register but never set currently */
|
|
break;
|
|
}
|
|
|
|
/* Update state for future DVSEC additions */
|
|
range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length);
|
|
cxl->dvsec_offset += length;
|
|
}
|
|
|
|
/* CXL r3.0 Section 8.2.4.19.7 CXL HDM Decoder n Control Register */
|
|
uint8_t cxl_interleave_ways_enc(int iw, Error **errp)
|
|
{
|
|
switch (iw) {
|
|
case 1: return 0x0;
|
|
case 2: return 0x1;
|
|
case 4: return 0x2;
|
|
case 8: return 0x3;
|
|
case 16: return 0x4;
|
|
case 3: return 0x8;
|
|
case 6: return 0x9;
|
|
case 12: return 0xa;
|
|
default:
|
|
error_setg(errp, "Interleave ways: %d not supported", iw);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp)
|
|
{
|
|
switch (iw_enc) {
|
|
case 0x0: return 1;
|
|
case 0x1: return 2;
|
|
case 0x2: return 4;
|
|
case 0x3: return 8;
|
|
case 0x4: return 16;
|
|
case 0x8: return 3;
|
|
case 0x9: return 6;
|
|
case 0xa: return 12;
|
|
default:
|
|
error_setg(errp, "Encoded interleave ways: %d not supported", iw_enc);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp)
|
|
{
|
|
switch (gran) {
|
|
case 256: return 0;
|
|
case 512: return 1;
|
|
case 1024: return 2;
|
|
case 2048: return 3;
|
|
case 4096: return 4;
|
|
case 8192: return 5;
|
|
case 16384: return 6;
|
|
default:
|
|
error_setg(errp, "Interleave granularity: %" PRIu64 " invalid", gran);
|
|
return 0;
|
|
}
|
|
}
|